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https://github.com/c64scene-ar/llvm-6502.git
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Clean up code for Mips16 large frame handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187701 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -10,7 +10,7 @@
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// This file contains the Mips16 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include <stdio.h>
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#include "Mips16InstrInfo.h"
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#include "InstPrinter/MipsInstPrinter.h"
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#include "MipsMachineFunction.h"
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@ -109,8 +109,9 @@ storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
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Opc = Mips::SwRxSpImmX16;
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assert(Opc && "Register class not handled!");
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BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
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BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).
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addFrameIndex(FI).addImm(Offset)
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.addMemOperand(MMO);
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}
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void Mips16InstrInfo::
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@ -323,48 +324,88 @@ Mips16InstrInfo::loadImmediate(unsigned FrameReg,
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//
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RegScavenger rs;
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int32_t lo = Imm & 0xFFFF;
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int32_t hi = ((Imm >> 16) + (lo >> 15)) & 0xFFFF;
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NewImm = lo;
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unsigned Reg =0;
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unsigned SpReg = 0;
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int Reg =0;
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int SpReg = 0;
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rs.enterBasicBlock(&MBB);
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rs.forward(II);
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//
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// We need to know which registers can be used, in the case where there
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// are not enough free registers. We exclude all registers that
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// are used in the instruction that we are helping.
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// // Consider all allocatable registers in the register class initially
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BitVector Candidates =
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RI.getAllocatableSet
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(*II->getParent()->getParent(), &Mips::CPU16RegsRegClass);
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// Exclude all the registers being used by the instruction.
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for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = II->getOperand(i);
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if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
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!TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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Candidates.reset(MO.getReg());
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}
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//
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// If the same register was used and defined in an instruction, then
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// it will not be in the list of candidates.
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//
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// we need to analyze the instruction that we are helping.
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// we need to know if it defines register x but register x is not
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// present as an operand of the instruction. this tells
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// whether the register is live before the instruction. if it's not
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// then we don't need to save it in case there are no free registers.
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//
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int DefReg = 0;
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for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = II->getOperand(i);
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if (MO.isReg() && MO.isDef()) {
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DefReg = MO.getReg();
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break;
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}
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}
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//
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BitVector Available = rs.getRegsAvailable(&Mips::CPU16RegsRegClass);
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Available &= Candidates;
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//
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// we use T0 for the first register, if we need to save something away.
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// we use T1 for the second register, if we need to save something away.
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//
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unsigned FirstRegSaved =0, SecondRegSaved=0;
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unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
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Reg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
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if (Reg == 0) {
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FirstRegSaved = Reg = Mips::V0;
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FirstRegSavedTo = Mips::T0;
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copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
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Reg = Available.find_first();
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if (Reg == -1) {
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Reg = Candidates.find_first();
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Candidates.reset(Reg);
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if (DefReg != Reg) {
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FirstRegSaved = Reg;
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FirstRegSavedTo = Mips::T0;
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copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
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}
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}
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else
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rs.setUsed(Reg);
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BuildMI(MBB, II, DL, get(Mips::LiRxImmX16), Reg).addImm(hi);
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BuildMI(MBB, II, DL, get(Mips::SllX16), Reg).addReg(Reg).
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addImm(16);
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Available.reset(Reg);
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BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm);
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NewImm = 0;
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if (FrameReg == Mips::SP) {
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SpReg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
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if (SpReg == 0) {
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if (Reg != Mips::V1) {
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SecondRegSaved = SpReg = Mips::V1;
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SpReg = Available.find_first();
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if (SpReg == -1) {
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SpReg = Candidates.find_first();
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// Candidates.reset(SpReg); // not really needed
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if (DefReg!= SpReg) {
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SecondRegSaved = SpReg;
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SecondRegSavedTo = Mips::T1;
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}
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else {
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SecondRegSaved = SpReg = Mips::V0;
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SecondRegSavedTo = Mips::T0;
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}
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copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
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if (SecondRegSaved)
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copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
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}
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else
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rs.setUsed(SpReg);
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else
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Available.reset(SpReg);
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copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
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BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg)
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BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg, RegState::Kill)
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.addReg(Reg);
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}
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else
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@ -380,6 +421,22 @@ Mips16InstrInfo::loadImmediate(unsigned FrameReg,
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return Reg;
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}
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/// This function generates the sequence of instructions needed to get the
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/// result of adding register REG and immediate IMM.
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unsigned
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Mips16InstrInfo::basicLoadImmediate(
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unsigned FrameReg,
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int64_t Imm, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator II, DebugLoc DL,
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unsigned &NewImm) const {
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const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;
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MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
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unsigned Reg = RegInfo.createVirtualRegister(RC);
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BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm);
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NewImm = 0;
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return Reg;
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}
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unsigned Mips16InstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
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return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 ||
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Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 ||
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@ -415,3 +472,27 @@ void Mips16InstrInfo::BuildAddiuSpImm
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const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
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return new Mips16InstrInfo(TM);
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}
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#include <stdio.h>
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bool Mips16InstrInfo::validImmediate(unsigned Opcode, unsigned Reg,
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int64_t Amount) {
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switch (Opcode) {
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case Mips::LbRxRyOffMemX16:
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case Mips::LbuRxRyOffMemX16:
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case Mips::LhRxRyOffMemX16:
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case Mips::LhuRxRyOffMemX16:
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case Mips::SbRxRyOffMemX16:
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case Mips::ShRxRyOffMemX16:
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case Mips::LwRxRyOffMemX16:
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case Mips::SwRxRyOffMemX16:
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case Mips::SwRxSpImmX16:
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case Mips::LwRxSpImmX16:
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return isInt<16>(Amount);
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case Mips::AddiuRxRyOffMemX16:
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if ((Reg == Mips::PC) || (Reg == Mips::SP))
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return isInt<16>(Amount);
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return isInt<15>(Amount);
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}
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printf("Unexpected opcode %i \n", Opcode);
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llvm_unreachable("unexpected Opcode in validImmediate");
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}
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@ -68,7 +68,7 @@ public:
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// Adjust SP by FrameSize bytes. Save RA, S0, S1
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void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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MachineBasicBlock::iterator I) const;
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// Adjust SP by FrameSize bytes. Restore RA, S0, S1
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void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
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@ -88,6 +88,13 @@ public:
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MachineBasicBlock::iterator II, DebugLoc DL,
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unsigned &NewImm) const;
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unsigned basicLoadImmediate(unsigned FrameReg,
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int64_t Imm, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator II, DebugLoc DL,
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unsigned &NewImm) const;
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static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount);
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static bool validSpImm8(int offset) {
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return ((offset & 7) == 0) && isInt<11>(offset);
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}
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// Address operand
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def mem16 : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops CPU16Regs, simm16, CPU16Regs);
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let MIOperandInfo = (ops CPU16Regs, simm16, CPU16RegsPlusSP);
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let EncoderMethod = "getMemEncoding";
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}
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def mem16_ea : Operand<i32> {
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let PrintMethod = "printMemOperandEA";
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let MIOperandInfo = (ops CPU16Regs, simm16);
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let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
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let EncoderMethod = "getMemEncoding";
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}
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@ -187,6 +187,11 @@ class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr,
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FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
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!strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
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class FEXT_RI16_SP_Store_explicit_ins<bits<5> _op, string asmstr,
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InstrItinClass itin>:
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FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, CPUSPReg:$ry, simm16:$imm),
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!strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
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//
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// EXT-RRI instruction format
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//
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@ -437,7 +442,7 @@ def Constant32:
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MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>;
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def LwConstant32:
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MipsPseudo16<(outs), (ins CPU16Regs:$rx, imm32:$imm),
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MipsPseudo16<(outs CPU16Regs:$rx), (ins imm32:$imm),
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"lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
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@ -1196,7 +1201,8 @@ def SwRxRyOffMemX16:
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// Purpose: Store Word rx (SP-Relative)
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// To store an SP-relative word to memory.
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//
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def SwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b11010, "sw", IIStore>, MayStore;
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def SwRxSpImmX16: FEXT_RI16_SP_Store_explicit_ins
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<0b11010, "sw", IIStore>, MayStore;
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//
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//
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DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
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if (!MI.isDebugValue() && ( ((FrameReg != Mips::SP) && !isInt<16>(Offset)) ||
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((FrameReg == Mips::SP) && !isInt<15>(Offset)) )) {
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if (!MI.isDebugValue() &&
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!Mips16InstrInfo::validImmediate(MI.getOpcode(), FrameReg, Offset)) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = II->getDebugLoc();
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unsigned NewImm;
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@ -159,6 +159,8 @@ getReservedRegs(const MachineFunction &MF) const {
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if (Subtarget.inMips16Mode()) {
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Reserved.set(Mips::RA);
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Reserved.set(Mips::RA_64);
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Reserved.set(Mips::T0);
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Reserved.set(Mips::T1);
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}
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// Reserve GP if small section is used.
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// Callee save
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S0, S1)>;
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def CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add
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// Return Values and Arguments
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V0, V1, A0, A1, A2, A3,
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// Callee save
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S0, S1,
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SP)>;
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def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable;
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def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;
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@ -1,5 +1,6 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -mips16-hard-float -soft-float -relocation-model=static < %s | FileCheck %s -check-prefix=1
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@i = common global i32 0, align 4
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@j = common global i32 0, align 4
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@.str = private unnamed_addr constant [8 x i8] c"%i %i \0A\00", align 1
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@ -24,20 +25,32 @@ define i32 @main() nounwind {
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entry:
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; 1-LABEL: main:
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; 1: 1: .word -797992
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; 1: li ${{[0-9]+}}, 12
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; 1: sll ${{[0-9]+}}, ${{[0-9]+}}, 16
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; 1: lw ${{[0-9]+}}, 1f
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; 1: b 2f
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; 1: .align 2
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; 1: .word 800016
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; 1: b 2f
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; 1: .align 2
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; 1: .word 400016
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; 1: move ${{[0-9]+}}, $sp
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; 1: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
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; 2: move $sp, ${{[0-9]+}}
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; 2: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
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; 1: li ${{[0-9]+}}, 6
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; 1: sll ${{[0-9]+}}, ${{[0-9]+}}, 16
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; 1: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0
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; 1: b 2f
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; 1: .align 2
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; 1: .word 400216
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; 1: move ${{[0-9]+}}, $sp
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; 1: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
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; 2: move $sp, ${{[0-9]+}}
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; 2: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
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; 1: addiu ${{[0-9]+}}, ${{[0-9]+}}, 6800
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; 1: li ${{[0-9]+}}, 1
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; 1: sll ${{[0-9]+}}, ${{[0-9]+}}, 16
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; 2: li ${{[0-9]+}}, 34463
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; 1: lw ${{[0-9]+}}, 0(${{[0-9]+}})
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%retval = alloca i32, align 4
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%one = alloca [100000 x i32], align 4
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%two = alloca [100000 x i32], align 4
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