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fold setcc of a setcc.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30953 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2006-10-14 01:02:29 +00:00
parent 51dabfb283
commit 8ac9d0ebde
1 changed files with 40 additions and 24 deletions
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28
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@@ -3685,15 +3685,29 @@ SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
ExtDstTy), ExtDstTy),
Cond); Cond);
} else if ((N1C->getValue() == 0 || N1C->getValue() == 1) && } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
(Cond == ISD::SETEQ || Cond == ISD::SETNE) && (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
(N0.getOpcode() == ISD::XOR ||
// SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
if (N0.getOpcode() == ISD::SETCC) {
bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1);
if (TrueWhenTrue)
return N0;
// Invert the condition.
ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
CC = ISD::getSetCCInverse(CC,
MVT::isInteger(N0.getOperand(0).getValueType()));
return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC);
}
if ((N0.getOpcode() == ISD::XOR ||
(N0.getOpcode() == ISD::AND && (N0.getOpcode() == ISD::AND &&
N0.getOperand(0).getOpcode() == ISD::XOR && N0.getOperand(0).getOpcode() == ISD::XOR &&
N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
isa<ConstantSDNode>(N0.getOperand(1)) && isa<ConstantSDNode>(N0.getOperand(1)) &&
cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) { cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
// If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
// only do this if the top bits are known zero. // can only do this if the top bits are known zero.
if (TLI.MaskedValueIsZero(N1, if (TLI.MaskedValueIsZero(N1,
MVT::getIntVTBitMask(N0.getValueType())-1)){ MVT::getIntVTBitMask(N0.getValueType())-1)){
// Okay, get the un-inverted input value. // Okay, get the un-inverted input value.
@@ -3705,12 +3719,14 @@ SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
N0.getOperand(0).getOpcode() == ISD::XOR); N0.getOperand(0).getOpcode() == ISD::XOR);
// ((X^1)&1)^1 -> X & 1 // ((X^1)&1)^1 -> X & 1
Val = DAG.getNode(ISD::AND, N0.getValueType(), Val = DAG.getNode(ISD::AND, N0.getValueType(),
N0.getOperand(0).getOperand(0), N0.getOperand(1)); N0.getOperand(0).getOperand(0),
N0.getOperand(1));
} }
return DAG.getSetCC(VT, Val, N1, return DAG.getSetCC(VT, Val, N1,
Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
} }
} }
}
uint64_t MinVal, MaxVal; uint64_t MinVal, MaxVal;
unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
@@ -3804,7 +3820,7 @@ SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
} }
if (N0 == N1) { if (N0 == N1) {
// We can always fold X == Y for integer setcc's. // We can always fold X == X for integer setcc's.
if (MVT::isInteger(N0.getValueType())) if (MVT::isInteger(N0.getValueType()))
return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
unsigned UOF = ISD::getUnorderedFlavor(Cond); unsigned UOF = ISD::getUnorderedFlavor(Cond);