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Update the sparc backend to at least compile correctly with the new varargs stuff even if it's not all implemented yet.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9223 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2003-10-18 05:55:58 +00:00
parent 4c6654963d
commit 8ad3946d74
2 changed files with 16 additions and 4 deletions
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8
lib/Target/SparcV9/SparcV9.burg.in
View File

@@ -87,8 +87,9 @@ Xdefine PANIC printf
%term Call=CallOPCODE %term Call=CallOPCODE
%term Shl=ShlOPCODE %term Shl=ShlOPCODE
%term Shr=ShrOPCODE %term Shr=ShrOPCODE
%term VaArg=VarArgOPCODE %term VANext=VANextOPCODE
/* 32...46 are unused */ %term VAArg=VAArgOPCODE
/* 33...46 are unused */
/* /*
* The foll. values should match the constants in InstrForest.h * The foll. values should match the constants in InstrForest.h
*/ */
@@ -258,7 +259,8 @@ reg: Call = 61 (20); /* just ignore the operands! */
reg: Shl(reg,reg) = 62 (20); /* 1 for issue restrictions */ reg: Shl(reg,reg) = 62 (20); /* 1 for issue restrictions */
reg: Shr(reg,reg) = 63 (20); /* 1 for issue restrictions */ reg: Shr(reg,reg) = 63 (20); /* 1 for issue restrictions */
reg: Phi(reg,reg) = 64 (0); reg: Phi(reg,reg) = 64 (0);
reg: VaArg(reg) = 65 (40); /* load from stack then incr */ reg: VANext(reg) = 65 (40); /* incr stack slot pointer */
reg: VAArg(reg) = 66 (40); /* get a vararg */
/* /*
* Finally, leaf nodes of expression trees. * Finally, leaf nodes of expression trees.

12
lib/Target/SparcV9/SparcV9InstrSelection.cpp
View File

@@ -1408,6 +1408,9 @@ bool CodeGenIntrinsic(LLVMIntrinsic::ID iid, CallInst &callInstr,
{ {
switch (iid) { switch (iid) {
case LLVMIntrinsic::va_start: { case LLVMIntrinsic::va_start: {
// FIXME: this needs to be updated!
abort();
// Get the address of the first vararg value on stack and copy it to // Get the address of the first vararg value on stack and copy it to
// the argument of va_start(va_list* ap). // the argument of va_start(va_list* ap).
bool ignore; bool ignore;
@@ -1426,6 +1429,9 @@ bool CodeGenIntrinsic(LLVMIntrinsic::ID iid, CallInst &callInstr,
return true; // no-op on Sparc return true; // no-op on Sparc
case LLVMIntrinsic::va_copy: case LLVMIntrinsic::va_copy:
// FIXME: this needs to be updated!
abort();
// Simple copy of current va_list (arg2) to new va_list (arg1) // Simple copy of current va_list (arg2) to new va_list (arg1)
mvec.push_back(BuildMI(V9::ORr, 3). mvec.push_back(BuildMI(V9::ORr, 3).
addMReg(target.getRegInfo().getZeroRegNum()). addMReg(target.getRegInfo().getZeroRegNum()).
@@ -2829,8 +2835,11 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
case 64: // reg: Phi(reg,reg) case 64: // reg: Phi(reg,reg)
break; // don't forward the value break; // don't forward the value
case 65: // reg: VaArg(reg): the va_arg instruction case 65: // reg: VANext(reg): the va_next instruction
case 66: // reg: VAArg (reg): the va_arg instruction
{ {
abort(); // FIXME: This is incorrect!
#if 0
// Use value initialized by va_start as pointer to args on the stack. // Use value initialized by va_start as pointer to args on the stack.
// Load argument via current pointer value, then increment pointer. // Load argument via current pointer value, then increment pointer.
int argSize = target.getFrameInfo().getSizeOfEachArgOnStack(); int argSize = target.getFrameInfo().getSizeOfEachArgOnStack();
@@ -2842,6 +2851,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
mvec.push_back(BuildMI(V9::ADDi, 3).addReg(vaArgI->getOperand(0)). mvec.push_back(BuildMI(V9::ADDi, 3).addReg(vaArgI->getOperand(0)).
addSImm(argSize).addRegDef(vaArgI->getOperand(0))); addSImm(argSize).addRegDef(vaArgI->getOperand(0)));
break; break;
#endif
} }
case 71: // reg: VReg case 71: // reg: VReg