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ARM: Fix fast-isel copy/paste-o.

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Update testcase to be more careful about checking register
values. While regexes are general goodness for these sorts of
testcases, in this example, the registers are constrained by
the calling convention, so we can and should check their
explicit values.

rdar://14779513

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188819 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2013-08-20 19:12:42 +00:00
parent 11873fc85a
commit 8b262e5ab8
2 changed files with 7 additions and 6 deletions
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2
lib/Target/ARM/ARMFastISel.cpp
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@ -1762,7 +1762,7 @@ bool ARMFastISel::SelectSelect(const Instruction *I) {
}
unsigned ResultReg = createResultReg(RC);
if (!UseImm) {
Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1);
Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1);
Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
.addReg(Op2Reg).addReg(Op1Reg).addImm(ARMCC::NE).addReg(ARM::CPSR);

11
test/CodeGen/ARM/fast-isel-select.ll
View File

@ -39,15 +39,16 @@ define i32 @t3(i1 %c, i32 %a, i32 %b) nounwind readnone {
entry:
; ARM: t3
; ARM: cmp r0, #0
; ARM: movne r{{[1-9]}}, r{{[1-9]}}
; ARM: mov r0, r{{[1-9]}}
; ARM: movne r2, r1
; ARM: add r0, r2, r1
; THUMB: t3
; THUMB: cmp r0, #0
; THUMB: it ne
; THUMB: movne r{{[1-9]}}, r{{[1-9]}}
; THUMB: mov r0, r{{[1-9]}}
; THUMB: movne r2, r1
; THUMB: add.w r0, r2, r1
%0 = select i1 %c, i32 %a, i32 %b
ret i32 %0
%1 = add i32 %0, %a
ret i32 %1
}
define i32 @t4(i1 %c) nounwind readnone {