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Match this pattern so that we can generate simpler code:
%a = ... %b = and i32 %a, 2 %c = srl i32 %b, 1 %d = br i32 %c, into %a = ... %b = and %a, 2 %c = X86ISD::CMP %b, 0 %d = X86ISD::BRCOND %c ... This applies only when the AND constant value has one bit set and the SRL constant is equal to the log2 of the AND constant. The back-end is smart enough to convert the result into a TEST/JMP sequence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67728 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -5870,6 +5870,45 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
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CC = DAG.getConstant(CCode, MVT::i8);
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Cond = Cond.getOperand(0).getOperand(1);
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addTest = false;
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} else if (Cond.hasOneUse() && Cond.getOpcode() == ISD::SRL) {
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// Match this pattern so that we can generate simpler code:
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//
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// %a = ...
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// %b = and i32 %a, 2
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// %c = srl i32 %b, 1
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// %d = br i32 %c,
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//
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// into
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//
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// %a = ...
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// %b = and %a, 2
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// %c = X86ISD::CMP %b, 0
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// %d = X86ISD::BRCOND %c ...
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//
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// This applies only when the AND constant value has one bit set and the
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// SRL constant is equal to the log2 of the AND constant. The back-end is
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// smart enough to convert the result into a TEST/JMP sequence.
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SDValue Op0 = Cond.getOperand(0);
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SDValue Op1 = Cond.getOperand(1);
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if (Op0.getOpcode() == ISD::AND &&
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Op0.hasOneUse() &&
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Op1.getOpcode() == ISD::Constant) {
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SDValue AndOp0 = Op0.getOperand(0);
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SDValue AndOp1 = Op0.getOperand(1);
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if (AndOp1.getOpcode() == ISD::Constant) {
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const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
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if (AndConst.isPowerOf2() &&
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cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
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CC = DAG.getConstant(X86::COND_NE, MVT::i8);
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Cond = EmitTest(Op0, X86::COND_NE, DAG);
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return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
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Chain, Dest, CC, Cond);
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}
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}
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}
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}
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}
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