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ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q

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and VDUPLN32d, respectively.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127486 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-03-11 20:31:17 +00:00
parent 1558df79b4
commit 8b8515c225
3 changed files with 10 additions and 12 deletions
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3
lib/Target/ARM/ARMExpandPseudoInsts.cpp
View File

@@ -1018,7 +1018,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
} }
case ARM::VDUPfqf: case ARM::VDUPfqf:
case ARM::VDUPfdf:{ case ARM::VDUPfdf:{
unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLNfq : ARM::VDUPLNfd; unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLN32q :
ARM::VDUPLN32d;
MachineInstrBuilder MIB = MachineInstrBuilder MIB =
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
unsigned OpIdx = 0; unsigned OpIdx = 0;

14
lib/Target/ARM/ARMInstrNEON.td
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@@ -4471,9 +4471,6 @@ def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16> {
def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32> { def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32> {
let Inst{19} = lane{0}; let Inst{19} = lane{0};
} }
def VDUPLNfd : VDUPLND<{?,1,0,0}, "vdup", "32", v2f32> {
let Inst{19} = lane{0};
}
def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8> { def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8> {
let Inst{19-17} = lane{2-0}; let Inst{19-17} = lane{2-0};
} }
@@ -4483,9 +4480,12 @@ def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16> {
def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32> { def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32> {
let Inst{19} = lane{0}; let Inst{19} = lane{0};
} }
def VDUPLNfq : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4f32, v2f32> {
let Inst{19} = lane{0}; def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
} (VDUPLN32d DPR:$Vm, imm:$lane)>;
def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
(VDUPLN32q DPR:$Vm, imm:$lane)>;
def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)), def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
(v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src, (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
@@ -4500,7 +4500,7 @@ def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
(DSubReg_i32_reg imm:$lane))), (DSubReg_i32_reg imm:$lane))),
(SubReg_i32_lane imm:$lane)))>; (SubReg_i32_lane imm:$lane)))>;
def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)), def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
(v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src, (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
(DSubReg_i32_reg imm:$lane))), (DSubReg_i32_reg imm:$lane))),
(SubReg_i32_lane imm:$lane)))>; (SubReg_i32_lane imm:$lane)))>;

5
utils/TableGen/ARMDecoderEmitter.cpp
View File

@@ -1654,16 +1654,13 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI,
Name == "VEXTq16" || Name == "VEXTq32" || Name == "VEXTqf") Name == "VEXTq16" || Name == "VEXTq32" || Name == "VEXTqf")
return false; return false;
// VDUPLNfd is equivalent to VDUPLN32d.
// VDUPLNfq is equivalent to VDUPLN32q.
// VLD1df is equivalent to VLD1d32. // VLD1df is equivalent to VLD1d32.
// VLD1qf is equivalent to VLD1q32. // VLD1qf is equivalent to VLD1q32.
// VLD2d64 is equivalent to VLD1q64. // VLD2d64 is equivalent to VLD1q64.
// VST1df is equivalent to VST1d32. // VST1df is equivalent to VST1d32.
// VST1qf is equivalent to VST1q32. // VST1qf is equivalent to VST1q32.
// VST2d64 is equivalent to VST1q64. // VST2d64 is equivalent to VST1q64.
if (Name == "VDUPLNfd" || Name == "VDUPLNfq" || if (Name == "VLD1df" || Name == "VLD1qf" || Name == "VLD2d64" ||
Name == "VLD1df" || Name == "VLD1qf" || Name == "VLD2d64" ||
Name == "VST1df" || Name == "VST1qf" || Name == "VST2d64") Name == "VST1df" || Name == "VST1qf" || Name == "VST2d64")
return false; return false;
} else if (TN == TARGET_THUMB) { } else if (TN == TARGET_THUMB) {