From 8b91c77385a055474d271aa8c10f0382fdeaafeb Mon Sep 17 00:00:00 2001 From: Andrew Lenharth Date: Fri, 11 Nov 2005 22:48:54 +0000 Subject: [PATCH] added a chain output git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24306 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/SelectionDAGNodes.h | 3 +++ lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 12 ++++++++++-- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index 94ef5d5901f..3af9008a436 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -308,6 +308,9 @@ namespace ISD { PCMARKER, // READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic. + // The only operand is a chain and a value and a chain are produced. The + // value is the contents of the architecture specific cycle counter like + // register (or other high accuracy low latency clock source) READCYCLECOUNTER, // READPORT, WRITEPORT, READIO, WRITEIO - These correspond to the LLVM diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index ae61e208963..01e76c1b423 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -804,9 +804,17 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); return 0; } - case Intrinsic::readcyclecounter: - setValue(&I, DAG.getNode(ISD::READCYCLECOUNTER, MVT::i64, getRoot())); + case Intrinsic::readcyclecounter: { + std::vector VTs; + VTs.push_back(MVT::i64); + VTs.push_back(MVT::Other); + std::vector Ops; + Ops.push_back(getRoot()); + SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, VTs, Ops); + setValue(&I, Tmp); + DAG.setRoot(Tmp.getValue(1)); return 0; + } case Intrinsic::cttz: setValue(&I, DAG.getNode(ISD::CTTZ, getValue(I.getOperand(1)).getValueType(),