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XCore target: implement exception handling

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194564 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Robert Lytton 2013-11-13 10:19:31 +00:00
parent cb92f8ecc9
commit 8b99622b9b
5 changed files with 176 additions and 11 deletions
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2
lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp
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@ -30,5 +30,7 @@ XCoreMCAsmInfo::XCoreMCAsmInfo(StringRef TT) {
// Debug
HasLEB128 = true;
ExceptionsType = ExceptionHandling::DwarfCFI;
DwarfRegNumForCFI = true;
}

36
lib/Target/XCore/XCoreFrameLowering.cpp
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@ -88,6 +88,7 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const {
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
MachineModuleInfo *MMI = &MF.getMMI();
const MCRegisterInfo *MRI = MMI->getContext().getRegisterInfo();
const XCoreInstrInfo &TII =
*static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo());
XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
@ -119,21 +120,28 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const {
bool saveLR = XFI->getUsesLR();
// Do we need to allocate space on the stack?
if (FrameSize) {
bool LRSavedOnEntry = false;
int Opcode;
if (saveLR && (MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0)) {
Opcode = (isU6) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
MBB.addLiveIn(XCore::LR);
saveLR = false;
LRSavedOnEntry = true;
} else {
Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
}
BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
if (emitFrameMoves) {
// Show update of SP.
MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol();
BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
MMI->addFrameInst(MCCFIInstruction::createDefCfaOffset(FrameLabel,
-FrameSize*4));
if (LRSavedOnEntry) {
unsigned Reg = MRI->getDwarfRegNum(XCore::LR, true);
MMI->addFrameInst(MCCFIInstruction::createOffset(FrameLabel, Reg, 0));
}
}
}
if (saveLR) {
@ -144,6 +152,9 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const {
if (emitFrameMoves) {
MCSymbol *SaveLRLabel = MMI->getContext().CreateTempSymbol();
BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLRLabel);
unsigned Reg = MRI->getDwarfRegNum(XCore::LR, true);
MMI->addFrameInst(MCCFIInstruction::createOffset(SaveLRLabel, Reg,
LRSpillOffset));
}
}
@ -156,15 +167,34 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const {
if (emitFrameMoves) {
MCSymbol *SaveR10Label = MMI->getContext().CreateTempSymbol();
BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveR10Label);
unsigned Reg = MRI->getDwarfRegNum(XCore::R10, true);
MMI->addFrameInst(MCCFIInstruction::createOffset(SaveR10Label, Reg,
FPSpillOffset));
}
// Set the FP from the SP.
unsigned FramePtr = XCore::R10;
BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr)
.addImm(0);
BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr).addImm(0);
if (emitFrameMoves) {
// Show FP is now valid.
MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol();
BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
unsigned Reg = MRI->getDwarfRegNum(FramePtr, true);
MMI->addFrameInst(MCCFIInstruction::createDefCfaRegister(FrameLabel,
Reg));
}
}
if (emitFrameMoves) {
// Frame moves for callee saved.
std::vector<std::pair<MCSymbol*, CalleeSavedInfo> >&SpillLabels =
XFI->getSpillLabels();
for (unsigned I = 0, E = SpillLabels.size(); I != E; ++I) {
MCSymbol *SpillLabel = SpillLabels[I].first;
CalleeSavedInfo &CSI = SpillLabels[I].second;
int Offset = MFI->getObjectOffset(CSI.getFrameIdx());
unsigned Reg = MRI->getDwarfRegNum(CSI.getReg(), true);
MMI->addFrameInst(MCCFIInstruction::createOffset(SpillLabel, Reg,
Offset));
}
}
}

4
lib/Target/XCore/XCoreISelLowering.cpp
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@ -149,6 +149,10 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM)
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
// Exception handling
setExceptionPointerRegister(XCore::R0);
setExceptionSelectorRegister(XCore::R1);
// Atomic operations
setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);

16
test/CodeGen/XCore/ashr.ll
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@ -1,26 +1,26 @@
; RUN: llc < %s -march=xcore -asm-verbose=0 | FileCheck %s
define i32 @ashr(i32 %a, i32 %b) {
define i32 @ashr(i32 %a, i32 %b) nounwind {
%1 = ashr i32 %a, %b
ret i32 %1
}
; CHECK-LABEL: ashr:
; CHECK-NEXT: ashr r0, r0, r1
define i32 @ashri1(i32 %a) {
define i32 @ashri1(i32 %a) nounwind {
%1 = ashr i32 %a, 24
ret i32 %1
}
; CHECK-LABEL: ashri1:
; CHECK-NEXT: ashr r0, r0, 24
define i32 @ashri2(i32 %a) {
define i32 @ashri2(i32 %a) nounwind {
%1 = ashr i32 %a, 31
ret i32 %1
}
; CHECK-LABEL: ashri2:
; CHECK-NEXT: ashr r0, r0, 32
define i32 @f1(i32 %a) {
define i32 @f1(i32 %a) nounwind nounwind {
%1 = icmp slt i32 %a, 0
br i1 %1, label %less, label %not_less
less:
@ -32,7 +32,7 @@ not_less:
; CHECK-NEXT: ashr r0, r0, 32
; CHECK-NEXT: bt r0
define i32 @f2(i32 %a) {
define i32 @f2(i32 %a) nounwind {
%1 = icmp sge i32 %a, 0
br i1 %1, label %greater, label %not_greater
greater:
@ -44,7 +44,7 @@ not_greater:
; CHECK-NEXT: ashr r0, r0, 32
; CHECK-NEXT: bt r0
define i32 @f3(i32 %a) {
define i32 @f3(i32 %a) nounwind {
%1 = icmp slt i32 %a, 0
%2 = select i1 %1, i32 10, i32 17
ret i32 %2
@ -55,7 +55,7 @@ define i32 @f3(i32 %a) {
; CHECK-NEXT: ldc r0, 17
; CHECK: ldc r0, 10
define i32 @f4(i32 %a) {
define i32 @f4(i32 %a) nounwind {
%1 = icmp sge i32 %a, 0
%2 = select i1 %1, i32 10, i32 17
ret i32 %2
@ -66,7 +66,7 @@ define i32 @f4(i32 %a) {
; CHECK-NEXT: ldc r0, 10
; CHECK: ldc r0, 17
define i32 @f5(i32 %a) {
define i32 @f5(i32 %a) nounwind {
%1 = icmp sge i32 %a, 0
%2 = zext i1 %1 to i32
ret i32 %2

129
test/CodeGen/XCore/exception.ll Normal file
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@ -0,0 +1,129 @@
; RUN: llc < %s -march=xcore | FileCheck %s
declare void @g()
declare i32 @__gxx_personality_v0(...)
declare i32 @llvm.eh.typeid.for(i8*) nounwind readnone
declare i8* @__cxa_begin_catch(i8*)
declare void @__cxa_end_catch()
declare i8* @__cxa_allocate_exception(i32)
declare void @__cxa_throw(i8*, i8*, i8*)
@_ZTIi = external constant i8*
@_ZTId = external constant i8*
; CHECK-LABEL: fn_typeid:
; CHECK: .cfi_startproc
; CHECK: mkmsk r0, 1
; CHECK: retsp 0
; CHECK: .cfi_endproc
define i32 @fn_typeid() {
entry:
%0 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*)) nounwind
ret i32 %0
}
; CHECK-LABEL: fn_throw
; CHECK: .cfi_startproc
; CHECK: entsp 1
; CHECK: .cfi_def_cfa_offset 4
; CHECK: .cfi_offset 15, 0
; CHECK: ldc r0, 4
; CHECK: bl __cxa_allocate_exception
; CHECK: ldaw r11, cp[_ZTIi]
; CHECK: ldc r2, 0
; CHECK: mov r1, r11
; CHECK: bl __cxa_throw
define void @fn_throw() {
entry:
%0 = call i8* @__cxa_allocate_exception(i32 4) nounwind
call void @__cxa_throw(i8* %0, i8* bitcast (i8** @_ZTIi to i8*), i8* null) noreturn
unreachable
}
; CHECK-LABEL: fn_catch
; CHECK: .cfi_startproc
; CHECK: .cfi_personality 0, __gxx_personality_v0
; CHECK: [[START:.L[a-zA-Z0-9_]+]]
; CHECK: .cfi_lsda 0, [[LSDA:.L[a-zA-Z0-9_]+]]
; CHECK: entsp 4
; CHECK: .cfi_def_cfa_offset 16
; CHECK: .cfi_offset 15, 0
define void @fn_catch() {
entry:
; N.B. we alloc no variables, hence force compiler to spill
; CHECK: stw r4, sp[3]
; CHECK: .cfi_offset 4, -4
; CHECK: stw r5, sp[2]
; CHECK: .cfi_offset 5, -8
; CHECK: stw r6, sp[1]
; CHECK: .cfi_offset 6, -12
; CHECK: [[PRE_G:.L[a-zA-Z0-9_]+]]
; CHECK: bl g
; CHECK: [[POST_G:.L[a-zA-Z0-9_]+]]
; CHECK: [[RETURN:.L[a-zA-Z0-9_]+]]
; CHECK: ldw r6, sp[1]
; CHECK: ldw r5, sp[2]
; CHECK: ldw r4, sp[3]
; CHECK: retsp 4
invoke void @g() to label %cont unwind label %lpad
cont:
ret void
; CHECK: {{.L[a-zA-Z0-9_]+}}
; CHECK: [[LANDING:.L[a-zA-Z0-9_]+]]
; CHECK: mov r5, r1
; CHECK: mov r4, r0
; CHECK: bl __cxa_begin_catch
; CHECK: ldw r6, r0[0]
; CHECK: bl __cxa_end_catch
lpad:
%0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
catch i8* bitcast (i8** @_ZTIi to i8*)
catch i8* bitcast (i8** @_ZTId to i8*)
%1 = extractvalue { i8*, i32 } %0, 0
%2 = extractvalue { i8*, i32 } %0, 1
%3 = call i8* @__cxa_begin_catch(i8* %1) nounwind
%4 = bitcast i8* %3 to i32*
%5 = load i32* %4
call void @__cxa_end_catch() nounwind
; CHECK: eq r0, r6, r5
; CHECK: bf r0, [[RETURN]]
; CHECK: mov r0, r4
; CHECK: bl _Unwind_Resume
; CHECK: .cfi_endproc
; CHECK: [[END:.L[a-zA-Z0-9_]+]]
%6 = icmp eq i32 %5, %2
br i1 %6, label %Resume, label %Exit
Resume:
resume { i8*, i32 } %0
Exit:
ret void
}
; CHECK: [[LSDA]]:
; CHECK: .byte 255
; CHECK: .byte 0
; CHECK: .asciiz
; CHECK: .byte 3
; CHECK: .byte 26
; CHECK: [[SET0:.L[a-zA-Z0-9_]+]] = [[PRE_G]]-[[START]]
; CHECK: .long [[SET0]]
; CHECK: [[SET1:.L[a-zA-Z0-9_]+]] = [[POST_G]]-[[PRE_G]]
; CHECK: .long [[SET1]]
; CHECK: [[SET2:.L[a-zA-Z0-9_]+]] = [[LANDING]]-[[START]]
; CHECK: .long [[SET2]]
; CHECK: .byte 3
; CHECK: [[SET3:.L[a-zA-Z0-9_]+]] = [[POST_G]]-[[START]]
; CHECK: .long [[SET3]]
; CHECK: [[SET4:.L[a-zA-Z0-9_]+]] = [[END]]-[[POST_G]]
; CHECK: .long [[SET4]]
; CHECK: .long 0
; CHECK: .byte 0
; CHECK: .byte 1
; CHECK: .byte 0
; CHECK: .byte 2
; CHECK: .byte 125
; CHECK: .long _ZTIi
; CHECK: .long _ZTId