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When remat'ing and destination virtual register has a sub-register index. Make sure the sub-register class matches the register class of the remat'ed instruction definition register class.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81204 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-09-08 06:39:07 +00:00
parent d19ceb9b12
commit 8bdb0de2bd
2 changed files with 64 additions and 0 deletions
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16
lib/CodeGen/SimpleRegisterCoalescing.cpp
View File

@ -660,6 +660,22 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
return false;
}
// If destination register has a sub-register index on it, make sure it mtches
// the instruction register class.
if (DstSubIdx) {
const TargetInstrDesc &TID = DefMI->getDesc();
if (TID.getNumDefs() != 1)
return false;
const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
const TargetRegisterClass *DstSubRC =
DstRC->getSubRegisterRegClass(DstSubIdx);
const TargetRegisterClass *DefRC = TID.OpInfo[0].getRegClass(tri_);
if (DefRC == DstRC)
DstSubIdx = 0;
else if (DefRC != DstSubRC)
return false;
}
MachineInstrIndex DefIdx = li_->getDefIndex(CopyIdx);
const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
DLR->valno->setCopy(0);

48
test/CodeGen/X86/2009-09-07-CoalescerBug.ll Normal file
View File

@ -0,0 +1,48 @@
; RUN: llvm-as < %s | llc -triple=x86_64-unknown-freebsd7.2 -code-model=kernel | FileCheck %s
; PR4689
%struct.__s = type { [8 x i8] }
%struct.pcb = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i16, i8* }
%struct.pcpu = type { i32*, i32*, i32*, i32*, %struct.pcb*, i64, i32, i32, i32, i32 }
define i64 @hammer_time(i64 %modulep, i64 %physfree) nounwind ssp noredzone noimplicitfloat {
; CHECK: hammer_time:
; CHECK: movq $Xrsvd, %rax
; CHECK: movq $Xrsvd, %rdi
; CHECK: movq $Xrsvd, %r8
entry:
br i1 undef, label %if.then, label %if.end
if.then: ; preds = %entry
br label %if.end
if.end: ; preds = %if.then, %entry
br label %for.body
for.body: ; preds = %for.inc, %if.end
switch i32 undef, label %if.then76 [
i32 9, label %for.inc
i32 10, label %for.inc
i32 11, label %for.inc
i32 12, label %for.inc
]
if.then76: ; preds = %for.body
unreachable
for.inc: ; preds = %for.body, %for.body, %for.body, %for.body
br i1 undef, label %for.end, label %for.body
for.end: ; preds = %for.inc
call void asm sideeffect "mov $1,%gs:$0", "=*m,r,~{dirflag},~{fpsr},~{flags}"(%struct.__s* bitcast (%struct.pcb** getelementptr (%struct.pcpu* null, i32 0, i32 4) to %struct.__s*), i64 undef) nounwind
br label %for.body170
for.body170: ; preds = %for.body170, %for.end
store i64 or (i64 and (i64 or (i64 ptrtoint (void (i32, i32, i32, i32)* @Xrsvd to i64), i64 2097152), i64 2162687), i64 or (i64 or (i64 and (i64 shl (i64 ptrtoint (void (i32, i32, i32, i32)* @Xrsvd to i64), i64 32), i64 -281474976710656), i64 140737488355328), i64 15393162788864)), i64* undef
br i1 undef, label %for.end175, label %for.body170
for.end175: ; preds = %for.body170
unreachable
}
declare void @Xrsvd(i32, i32, i32, i32) ssp noredzone noimplicitfloat