mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-01 00:11:00 +00:00
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146322 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Stepan Dyatkovskiy
parent
fed4d19edd
commit
8c0b807e8f
@ -468,13 +468,23 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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// v2f64 is legal so that QR subregs can be extracted as f64 elements, but
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// neither Neon nor VFP support any arithmetic operations on it.
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// The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
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// supported for v4f32.
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setOperationAction(ISD::FADD, MVT::v2f64, Expand);
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setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
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setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
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// FIXME: Code duplication: FDIV and FREM are expanded always, see
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// ARMTargetLowering::addTypeForNEON method for details.
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setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
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setOperationAction(ISD::FREM, MVT::v2f64, Expand);
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// FIXME: Create unittest.
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// In another words, find a way when "copysign" appears in DAG with vector
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// operands.
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setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
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// FIXME: Code duplication: SETCC has custom operation action, see
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// ARMTargetLowering::addTypeForNEON method for details.
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setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
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// FIXME: Create unittest for FNEG and for FABS.
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setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
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setOperationAction(ISD::FABS, MVT::v2f64, Expand);
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setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
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@ -487,11 +497,23 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
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setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
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setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
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// FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
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setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
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setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
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setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
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setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
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setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
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setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
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setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
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setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
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setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
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setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
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setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
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setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
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setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
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setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
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setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
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// Neon does not support some operations on v1i64 and v2i64 types.
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setOperationAction(ISD::MUL, MVT::v1i64, Expand);
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302
test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
Normal file
302
test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
Normal file
@ -0,0 +1,302 @@
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; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s
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@A = global <4 x float> <float 0., float 1., float 2., float 3.>
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define void @test_sqrt(<4 x float>* %X) nounwind {
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; CHECK: test_sqrt:
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; CHECK: movw r1, :lower16:{{.*}}
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; CHECK-NEXT: movt r1, :upper16:{{.*}}
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; CHECK: vldmia r1, {[[short0:s[0-9]+]], [[short1:s[0-9]+]], [[short2:s[0-9]+]], [[short3:s[0-9]+]]}
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; CHECK: vsqrt.f32 {{s[0-9]+}}, [[short3]]
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; CHECK: vsqrt.f32 {{s[0-9]+}}, [[short2]]
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; CHECK: vsqrt.f32 {{s[0-9]+}}, [[short1]]
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; CHECK: vsqrt.f32 {{s[0-9]+}}, [[short0]]
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; CHECK-NEXT: vstmia {{.*}}
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L.entry:
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%0 = load <4 x float>* @A, align 16
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%1 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %0)
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store <4 x float> %1, <4 x float>* %X, align 16
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ret void
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}
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declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) nounwind readonly
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define void @test_cos(<4 x float>* %X) nounwind {
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; CHECK: test_cos:
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; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
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; CHECK-NEXT: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia [[reg0]], {{.*}}
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl cosf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl cosf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl cosf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl cosf
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; CHECK: vstmia {{.*}}
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L.entry:
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%0 = load <4 x float>* @A, align 16
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%1 = call <4 x float> @llvm.cos.v4f32(<4 x float> %0)
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store <4 x float> %1, <4 x float>* %X, align 16
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ret void
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}
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declare <4 x float> @llvm.cos.v4f32(<4 x float>) nounwind readonly
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define void @test_exp(<4 x float>* %X) nounwind {
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; CHECK: test_exp:
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; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
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; CHECK-NEXT: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia [[reg0]], {{.*}}
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl expf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl expf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl expf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl expf
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; CHECK: vstmia {{.*}}
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L.entry:
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%0 = load <4 x float>* @A, align 16
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%1 = call <4 x float> @llvm.exp.v4f32(<4 x float> %0)
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store <4 x float> %1, <4 x float>* %X, align 16
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ret void
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}
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declare <4 x float> @llvm.exp.v4f32(<4 x float>) nounwind readonly
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define void @test_exp2(<4 x float>* %X) nounwind {
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; CHECK: test_exp2:
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; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
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; CHECK-NEXT: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia [[reg0]], {{.*}}
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl exp2f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl exp2f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl exp2f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl exp2f
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; CHECK: vstmia {{.*}}
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L.entry:
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%0 = load <4 x float>* @A, align 16
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%1 = call <4 x float> @llvm.exp2.v4f32(<4 x float> %0)
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store <4 x float> %1, <4 x float>* %X, align 16
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ret void
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}
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declare <4 x float> @llvm.exp2.v4f32(<4 x float>) nounwind readonly
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define void @test_log10(<4 x float>* %X) nounwind {
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; CHECK: test_log10:
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; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
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; CHECK-NEXT: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia [[reg0]], {{.*}}
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl log10f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl log10f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl log10f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl log10f
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; CHECK: vstmia {{.*}}
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L.entry:
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%0 = load <4 x float>* @A, align 16
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%1 = call <4 x float> @llvm.log10.v4f32(<4 x float> %0)
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store <4 x float> %1, <4 x float>* %X, align 16
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ret void
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}
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declare <4 x float> @llvm.log10.v4f32(<4 x float>) nounwind readonly
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define void @test_log(<4 x float>* %X) nounwind {
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; CHECK: test_log:
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; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
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; CHECK-NEXT: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia [[reg0]], {{.*}}
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl logf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl logf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl logf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl logf
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; CHECK: vstmia {{.*}}
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L.entry:
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%0 = load <4 x float>* @A, align 16
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%1 = call <4 x float> @llvm.log.v4f32(<4 x float> %0)
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store <4 x float> %1, <4 x float>* %X, align 16
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ret void
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}
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declare <4 x float> @llvm.log.v4f32(<4 x float>) nounwind readonly
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define void @test_log2(<4 x float>* %X) nounwind {
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; CHECK: test_log2:
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; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
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; CHECK-NEXT: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia [[reg0]], {{.*}}
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl log2f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl log2f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl log2f
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl log2f
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; CHECK: vstmia {{.*}}
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L.entry:
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%0 = load <4 x float>* @A, align 16
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%1 = call <4 x float> @llvm.log2.v4f32(<4 x float> %0)
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store <4 x float> %1, <4 x float>* %X, align 16
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ret void
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}
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declare <4 x float> @llvm.log2.v4f32(<4 x float>) nounwind readonly
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define void @test_pow(<4 x float>* %X) nounwind {
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; CHECK: test_pow:
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; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
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; CHECK-NEXT: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia [[reg0]], {{.*}}
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl powf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl powf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl powf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl powf
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; CHECK: vstmia {{.*}}
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L.entry:
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%0 = load <4 x float>* @A, align 16
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%1 = call <4 x float> @llvm.pow.v4f32(<4 x float> %0, <4 x float> <float 2., float 2., float 2., float 2.>)
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store <4 x float> %1, <4 x float>* %X, align 16
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ret void
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}
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declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>) nounwind readonly
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define void @test_powi(<4 x float>* %X) nounwind {
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; CHECK: test_powi:
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; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
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; CHECK-NEXT: movt [[reg0]], :upper16:{{.*}}
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; CHECK-NEXT: vldmia [[reg0]], {{.*}}
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; CHECK: vmul.f32 {{.*}}
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; CHECK: vstmia {{.*}}
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L.entry:
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%0 = load <4 x float>* @A, align 16
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%1 = call <4 x float> @llvm.powi.v4f32(<4 x float> %0, i32 2)
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store <4 x float> %1, <4 x float>* %X, align 16
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ret void
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}
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declare <4 x float> @llvm.powi.v4f32(<4 x float>, i32) nounwind readonly
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define void @test_sin(<4 x float>* %X) nounwind {
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; CHECK: test_sin:
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; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
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; CHECK-NEXT: movt [[reg0]], :upper16:{{.*}}
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; CHECK: vldmia [[reg0]], {{.*}}
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl sinf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl sinf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl sinf
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; CHECK: {{[v]?mov}} r0, {{[r|s][0-9]+}}
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; CHECK: bl sinf
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; CHECK: vstmia {{.*}}
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L.entry:
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%0 = load <4 x float>* @A, align 16
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%1 = call <4 x float> @llvm.sin.v4f32(<4 x float> %0)
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store <4 x float> %1, <4 x float>* %X, align 16
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ret void
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}
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declare <4 x float> @llvm.sin.v4f32(<4 x float>) nounwind readonly
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