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Change the default scheduler from Latency to ILP, since Latency

Browse Source 
is going away.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142810 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2011-10-24 17:45:02 +00:00
parent 1028132b90
commit 8c2d270ae8
18 changed files with 184 additions and 234 deletions
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2
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -610,7 +610,7 @@ TargetLowering::TargetLowering(const TargetMachine &tm,
ExceptionSelectorRegister = 0;
BooleanContents = UndefinedBooleanContent;
BooleanVectorContents = UndefinedBooleanContent;
SchedPreferenceInfo = Sched::Latency;
SchedPreferenceInfo = Sched::ILP;
JumpBufSize = 0;
JumpBufAlignment = 0;
MinFunctionAlignment = 0;

6
test/CodeGen/Alpha/2010-08-01-mulreduce64.ll
View File

@ -5,7 +5,7 @@ define fastcc i64 @getcount(i64 %s) {
ret i64 %tmp431
}
; CHECK: sll $16,33,$0
; CHECK-NEXT: sll $16,32,$1
; CHECK-NEXT: addq $0,$1,$0
; CHECK: sll $16,32,$0
; CHECK-NEXT: sll $16,33,$1
; CHECK-NEXT: addq $1,$0,$0

12
test/CodeGen/MBlaze/cc.ll
View File

@ -222,8 +222,8 @@ define void @testing() {
%tmp.12 = call i32 @params8_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
i32 6, i32 7, i32 8)
; CHECK: {{swi? .*, r1, 28}}
; CHECK: {{swi? .*, r1, 32}}
; CHECK: {{swi? .*, r1, 28}}
; CHECK: {{.* r5, .*, .*}}
; CHECK: {{.* r6, .*, .*}}
; CHECK: {{.* r7, .*, .*}}
@ -235,9 +235,9 @@ define void @testing() {
%tmp.13 = call i32 @params9_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
i32 6, i32 7, i32 8, i32 9)
; CHECK: {{swi? .*, r1, 28}}
; CHECK: {{swi? .*, r1, 32}}
; CHECK: {{swi? .*, r1, 36}}
; CHECK: {{swi? .*, r1, 32}}
; CHECK: {{swi? .*, r1, 28}}
; CHECK: {{.* r5, .*, .*}}
; CHECK: {{.* r6, .*, .*}}
; CHECK: {{.* r7, .*, .*}}
@ -249,10 +249,10 @@ define void @testing() {
%tmp.14 = call i32 @params10_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
i32 6, i32 7, i32 8, i32 9, i32 10)
; CHECK: {{swi? .*, r1, 28}}
; CHECK: {{swi? .*, r1, 32}}
; CHECK: {{swi? .*, r1, 36}}
; CHECK: {{swi? .*, r1, 40}}
; CHECK: {{swi? .*, r1, 36}}
; CHECK: {{swi? .*, r1, 32}}
; CHECK: {{swi? .*, r1, 28}}
; CHECK: {{.* r5, .*, .*}}
; CHECK: {{.* r6, .*, .*}}
; CHECK: {{.* r7, .*, .*}}

18
test/CodeGen/MBlaze/div.ll
View File

@ -13,14 +13,14 @@ define i8 @test_i8(i8 %a, i8 %b) {
; FUN-NOT: idiv
; FUN: brlid
; DIV-NOT: brlid
; DIV: idivu
; DIV: idiv
%tmp.2 = sdiv i8 %a, %b
; FUN-NOT: idiv
; FUN: brlid
; DIV-NOT: brlid
; DIV-NOT: idivu
; DIV: idiv
; DIV-NOT: idiv
; DIV: idivu
%tmp.3 = add i8 %tmp.1, %tmp.2
ret i8 %tmp.3
@ -36,14 +36,14 @@ define i16 @test_i16(i16 %a, i16 %b) {
; FUN-NOT: idiv
; FUN: brlid
; DIV-NOT: brlid
; DIV: idivu
; DIV: idiv
%tmp.2 = sdiv i16 %a, %b
; FUN-NOT: idiv
; FUN: brlid
; DIV-NOT: brlid
; DIV-NOT: idivu
; DIV: idiv
; DIV-NOT: idiv
; DIV: idivu
%tmp.3 = add i16 %tmp.1, %tmp.2
ret i16 %tmp.3
@ -59,14 +59,14 @@ define i32 @test_i32(i32 %a, i32 %b) {
; FUN-NOT: idiv
; FUN: brlid
; DIV-NOT: brlid
; DIV: idivu
; DIV: idiv
%tmp.2 = sdiv i32 %a, %b
; FUN-NOT: idiv
; FUN: brlid
; DIV-NOT: brlid
; DIV-NOT: idivu
; DIV: idiv
; DIV-NOT: idiv
; DIV: idivu
%tmp.3 = add i32 %tmp.1, %tmp.2
ret i32 %tmp.3

2
test/CodeGen/Mips/2010-07-20-Switch.ll
View File

@ -6,8 +6,8 @@ entry:
volatile store i32 2, i32* %x, align 4
%0 = volatile load i32* %x, align 4 ; <i32> [#uses=1]
; CHECK: lui $3, %hi($JTI0_0)
; CHECK: sll $2, $2, 2
; CHECK: addiu $3, $3, %lo($JTI0_0)
; CHECK: sll $2, $2, 2
switch i32 %0, label %bb4 [
i32 0, label %bb5
i32 1, label %bb1

4
test/CodeGen/Mips/cmov.ll
View File

@ -4,8 +4,8 @@
@i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
@i3 = common global i32* null, align 4
; CHECK: addiu ${{[0-9]+}}, $gp, %got(i1)
; CHECK: lw ${{[0-9]+}}, %got(i3)($gp)
; CHECK: addiu ${{[0-9]+}}, $gp, %got(i1)
define i32* @cmov1(i32 %s) nounwind readonly {
entry:
%tobool = icmp ne i32 %s, 0
@ -18,8 +18,8 @@ entry:
@d = global i32 0, align 4
; CHECK: cmov2:
; CHECK: addiu $[[R0:[0-9]+]], $gp, %got(c)
; CHECK: addiu $[[R1:[0-9]+]], $gp, %got(d)
; CHECK: addiu $[[R0:[0-9]+]], $gp, %got(c)
; CHECK: movn $[[R1]], $[[R0]], ${{[0-9]+}}
define i32 @cmov2(i32 %s) nounwind readonly {
entry:

4
test/CodeGen/Mips/eh.ll
View File

@ -10,15 +10,11 @@ entry:
; CHECK-EL: .cfi_def_cfa_offset
; CHECK-EL: sdc1 $f20
; CHECK-EL: sw $ra
; CHECK-EL: sw $17
; CHECK-EL: sw $16
; CHECK-EL: .cfi_offset 52, -8
; CHECK-EL: .cfi_offset 53, -4
; CHECK-EB: .cfi_offset 53, -8
; CHECK-EB: .cfi_offset 52, -4
; CHECK-EL: .cfi_offset 31, -12
; CHECK-EL: .cfi_offset 17, -16
; CHECK-EL: .cfi_offset 16, -20
; CHECK-EL: .cprestore
%exception = tail call i8* @__cxa_allocate_exception(i32 8) nounwind

34
test/CodeGen/Mips/fcopysign.ll
View File

@ -4,27 +4,27 @@
define double @func0(double %d0, double %d1) nounwind readnone {
entry:
; CHECK-EL: func0:
; CHECK-EL: lui $[[T0:[0-9]+]], 32767
; CHECK-EL: lui $[[T1:[0-9]+]], 32768
; CHECK-EL: mfc1 $[[HI0:[0-9]+]], $f13
; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
; CHECK-EL: mfc1 $[[HI1:[0-9]+]], $f15
; CHECK-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0
; CHECK-EL: and $[[AND0:[0-9]+]], $[[HI0]], $[[MSK0]]
; CHECK-EL: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]]
; CHECK-EL: mfc1 $[[LO0:[0-9]+]], $f12
; CHECK-EL: mfc1 $[[HI0:[0-9]+]], $f15
; CHECK-EL: and $[[AND1:[0-9]+]], $[[HI0]], $[[MSK1]]
; CHECK-EL: lui $[[T0:[0-9]+]], 32767
; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
; CHECK-EL: mfc1 $[[HI1:[0-9]+]], $f13
; CHECK-EL: and $[[AND0:[0-9]+]], $[[HI1]], $[[MSK0]]
; CHECK-EL: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
; CHECK-EL: mfc1 $[[LO0:[0-9]+]], $f12
; CHECK-EL: mtc1 $[[LO0]], $f0
; CHECK-EL: mtc1 $[[OR]], $f1
;
; CHECK-EB: lui $[[T0:[0-9]+]], 32767
; CHECK-EB: lui $[[T1:[0-9]+]], 32768
; CHECK-EB: mfc1 $[[HI0:[0-9]+]], $f12
; CHECK-EB: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
; CHECK-EB: mfc1 $[[HI1:[0-9]+]], $f14
; CHECK-EB: ori $[[MSK1:[0-9]+]], $[[T1]], 0
; CHECK-EB: and $[[AND0:[0-9]+]], $[[HI0]], $[[MSK0]]
; CHECK-EB: mfc1 $[[HI1:[0-9]+]], $f14
; CHECK-EB: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]]
; CHECK-EB: lui $[[T0:[0-9]+]], 32767
; CHECK-EB: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
; CHECK-EB: mfc1 $[[HI0:[0-9]+]], $f12
; CHECK-EB: and $[[AND0:[0-9]+]], $[[HI0]], $[[MSK0]]
; CHECK-EB: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
; CHECK-EB: mfc1 $[[LO0:[0-9]+]], $f13
; CHECK-EB: mtc1 $[[OR]], $f0
@ -38,14 +38,14 @@ declare double @copysign(double, double) nounwind readnone
define float @func1(float %f0, float %f1) nounwind readnone {
entry:
; CHECK-EL: func1:
; CHECK-EL: lui $[[T0:[0-9]+]], 32767
; CHECK-EL: lui $[[T1:[0-9]+]], 32768
; CHECK-EL: mfc1 $[[ARG0:[0-9]+]], $f12
; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
; CHECK-EL: mfc1 $[[ARG1:[0-9]+]], $f14
; CHECK-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0
; CHECK-EL: and $[[T2:[0-9]+]], $[[ARG0]], $[[MSK0]]
; CHECK-EL: mfc1 $[[ARG1:[0-9]+]], $f14
; CHECK-EL: and $[[T3:[0-9]+]], $[[ARG1]], $[[MSK1]]
; CHECK-EL: lui $[[T0:[0-9]+]], 32767
; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
; CHECK-EL: mfc1 $[[ARG0:[0-9]+]], $f12
; CHECK-EL: and $[[T2:[0-9]+]], $[[ARG0]], $[[MSK0]]
; CHECK-EL: or $[[T4:[0-9]+]], $[[T2]], $[[T3]]
; CHECK-EL: mtc1 $[[T4]], $f0
%call = tail call float @copysignf(float %f0, float %f1) nounwind readnone

18
test/CodeGen/Mips/fpcmp.ll
View File

@ -1,18 +0,0 @@
; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-MIPS32
@g1 = external global i32
define i32 @f(float %f0, float %f1) nounwind {
entry:
; CHECK-MIPS32: c.olt.s
; CHECK-MIPS32: movt
; CHECK-MIPS32: c.olt.s
; CHECK-MIPS32: movt
%cmp = fcmp olt float %f0, %f1
%conv = zext i1 %cmp to i32
%tmp2 = load i32* @g1, align 4
%add = add nsw i32 %tmp2, %conv
store i32 %add, i32* @g1, align 4
%cond = select i1 %cmp, i32 10, i32 20
ret i32 %cond
}

8
test/CodeGen/Mips/i64arg.ll
View File

@ -4,21 +4,21 @@ define void @f1(i64 %ll1, float %f, i64 %ll, i32 %i, float %f2) nounwind {
entry:
; CHECK: addu $[[R1:[0-9]+]], $zero, $5
; CHECK: addu $[[R0:[0-9]+]], $zero, $4
; CHECK: lw $25, %call16(ff1)
; CHECK: ori $6, ${{[0-9]+}}, 3855
; CHECK: ori $7, ${{[0-9]+}}, 22136
; CHECK: lw $25, %call16(ff1)
; CHECK: jalr
tail call void @ff1(i32 %i, i64 1085102592623924856) nounwind
; CHECK: lw $25, %call16(ff2)
; CHECK: lw $[[R2:[0-9]+]], 88($sp)
; CHECK: lw $[[R3:[0-9]+]], 92($sp)
; CHECK: lw $[[R2:[0-9]+]], 80($sp)
; CHECK: lw $[[R3:[0-9]+]], 84($sp)
; CHECK: addu $4, $zero, $[[R2]]
; CHECK: addu $5, $zero, $[[R3]]
; CHECK: jalr $25
tail call void @ff2(i64 %ll, double 3.000000e+00) nounwind
%sub = add nsw i32 %i, -1
; CHECK: sw $[[R0]], 24($sp)
; CHECK: sw $[[R1]], 28($sp)
; CHECK: sw $[[R0]], 24($sp)
; CHECK: lw $25, %call16(ff3)
; CHECK: addu $6, $zero, $[[R2]]
; CHECK: addu $7, $zero, $[[R3]]

2
test/CodeGen/Mips/inlineasmmemop.ll
View File

@ -8,10 +8,10 @@ entry:
; CHECK: #APP
; CHECK: sw $4, 0($[[T0]])
; CHECK: #NO_APP
; CHECK: lw $[[T1:[0-9]+]], %got(g1)($gp)
; CHECK: #APP
; CHECK: lw $[[T3:[0-9]+]], 0($[[T0]])
; CHECK: #NO_APP
; CHECK: lw $[[T1:[0-9]+]], %got(g1)($gp)
; CHECK: sw $[[T3]], 0($[[T1]])
%l1 = alloca i32, align 4

54
test/CodeGen/Mips/o32_cc_byval.ll
View File

@ -12,20 +12,20 @@ define void @f1() nounwind {
entry:
; CHECK: lw $[[R1:[0-9]+]], %got(f1.s1)($gp)
; CHECK: addiu $[[R0:[0-9]+]], $[[R1]], %lo(f1.s1)
; CHECK: lw $[[R2:[0-9]+]], 8($[[R0]])
; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]])
; CHECK: lw $[[R3:[0-9]+]], 16($[[R0]])
; CHECK: lw $[[R4:[0-9]+]], 20($[[R0]])
; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]])
; CHECK: lw $[[R6:[0-9]+]], 28($[[R0]])
; CHECK: sw $[[R2]], 16($sp)
; CHECK: sw $[[R7]], 20($sp)
; CHECK: sw $[[R3]], 24($sp)
; CHECK: sw $[[R4]], 28($sp)
; CHECK: sw $[[R5]], 32($sp)
; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]])
; CHECK: lw $[[R4:[0-9]+]], 20($[[R0]])
; CHECK: lw $[[R3:[0-9]+]], 16($[[R0]])
; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]])
; CHECK: lw $[[R2:[0-9]+]], 8($[[R0]])
; CHECK: sw $[[R6]], 36($sp)
; CHECK: lw $6, %lo(f1.s1)($[[R1]])
; CHECK: sw $[[R5]], 32($sp)
; CHECK: sw $[[R4]], 28($sp)
; CHECK: sw $[[R3]], 24($sp)
; CHECK: sw $[[R7]], 20($sp)
; CHECK: sw $[[R2]], 16($sp)
; CHECK: lw $7, 4($[[R0]])
; CHECK: lw $6, %lo(f1.s1)($[[R1]])
%agg.tmp10 = alloca %struct.S3, align 4
call void @callee1(float 2.000000e+01, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind
call void @callee2(%struct.S2* byval @f1.s2) nounwind
@ -44,20 +44,20 @@ declare void @callee3(float, %struct.S3* byval, %struct.S1* byval)
define void @f2(float %f, %struct.S1* nocapture byval %s1) nounwind {
entry:
; CHECK: addiu $sp, $sp, -56
; CHECK: sw $6, 64($sp)
; CHECK: sw $7, 68($sp)
; CHECK: sw $6, 64($sp)
; CHECK: lw $4, 88($sp)
; CHECK: ldc1 $f[[F0:[0-9]+]], 80($sp)
; CHECK: lw $[[R3:[0-9]+]], 72($sp)
; CHECK: lw $[[R4:[0-9]+]], 76($sp)
; CHECK: lw $[[R2:[0-9]+]], 68($sp)
; CHECK: lh $[[R1:[0-9]+]], 66($sp)
; CHECK: lb $[[R0:[0-9]+]], 64($sp)
; CHECK: lw $[[R3:[0-9]+]], 72($sp)
; CHECK: lw $[[R4:[0-9]+]], 76($sp)
; CHECK: lw $4, 88($sp)
; CHECK: sw $[[R3]], 16($sp)
; CHECK: sw $[[R4]], 20($sp)
; CHECK: sw $[[R2]], 24($sp)
; CHECK: sw $[[R1]], 28($sp)
; CHECK: sw $[[R0]], 32($sp)
; CHECK: sw $[[R1]], 28($sp)
; CHECK: sw $[[R2]], 24($sp)
; CHECK: sw $[[R4]], 20($sp)
; CHECK: sw $[[R3]], 16($sp)
; CHECK: mfc1 $6, $f[[F0]]
%i2 = getelementptr inbounds %struct.S1* %s1, i32 0, i32 5
@ -81,12 +81,12 @@ declare void @callee4(i32, double, i64, i32, i16 signext, i8 signext, float)
define void @f3(%struct.S2* nocapture byval %s2) nounwind {
entry:
; CHECK: addiu $sp, $sp, -56
; CHECK: sw $4, 56($sp)
; CHECK: sw $5, 60($sp)
; CHECK: sw $6, 64($sp)
; CHECK: sw $7, 68($sp)
; CHECK: lw $[[R0:[0-9]+]], 68($sp)
; CHECK: sw $6, 64($sp)
; CHECK: sw $5, 60($sp)
; CHECK: sw $4, 56($sp)
; CHECK: lw $4, 56($sp)
; CHECK: lw $[[R0:[0-9]+]], 68($sp)
; CHECK: sw $[[R0]], 24($sp)
%arrayidx = getelementptr inbounds %struct.S2* %s2, i32 0, i32 0, i32 0
@ -100,14 +100,14 @@ entry:
define void @f4(float %f, %struct.S3* nocapture byval %s3, %struct.S1* nocapture byval %s1) nounwind {
entry:
; CHECK: addiu $sp, $sp, -56
; CHECK: sw $5, 60($sp)
; CHECK: sw $6, 64($sp)
; CHECK: sw $7, 68($sp)
; CHECK: sw $6, 64($sp)
; CHECK: sw $5, 60($sp)
; CHECK: lw $4, 68($sp)
; CHECK: lw $[[R1:[0-9]+]], 88($sp)
; CHECK: lb $[[R0:[0-9]+]], 60($sp)
; CHECK: lw $4, 68($sp)
; CHECK: sw $[[R1]], 24($sp)
; CHECK: sw $[[R0]], 32($sp)
; CHECK: sw $[[R1]], 24($sp)
%i = getelementptr inbounds %struct.S1* %s1, i32 0, i32 2
%tmp = load i32* %i, align 4, !tbaa !0

14
test/CodeGen/Mips/unalignedload.ll
View File

@ -9,27 +9,27 @@
define void @foo1() nounwind {
entry:
; CHECK-EL: lw $25, %call16(foo2)
; CHECK-EL: ulhu $4, 2
; CHECK-EL: lw $25, %call16(foo2)
; CHECK-EL: lw $[[R0:[0-9]+]], %got(s4)
; CHECK-EL: lbu $[[R1:[0-9]+]], 6($[[R0]])
; CHECK-EL: ulhu $[[R2:[0-9]+]], 4($[[R0]])
; CHECK-EL: sll $[[R3:[0-9]+]], $[[R1]], 16
; CHECK-EL: ulhu $[[R2:[0-9]+]], 4($[[R0]])
; CHECK-EL: or $5, $[[R2]], $[[R3]]
; CHECK-EL: ulw $4, 0($[[R0]])
; CHECK-EL: lw $25, %call16(foo4)
; CHECK-EL: or $5, $[[R2]], $[[R3]]
; CHECK-EB: ulhu $[[R0:[0-9]+]], 2
; CHECK-EB: lw $25, %call16(foo2)
; CHECK-EB: sll $4, $[[R0]], 16
; CHECK-EB: lw $25, %call16(foo2)
; CHECK-EB: lw $[[R1:[0-9]+]], %got(s4)
; CHECK-EB: ulhu $[[R2:[0-9]+]], 4($[[R1]])
; CHECK-EB: lbu $[[R3:[0-9]+]], 6($[[R1]])
; CHECK-EB: sll $[[R4:[0-9]+]], $[[R2]], 16
; CHECK-EB: sll $[[R5:[0-9]+]], $[[R3]], 8
; CHECK-EB: ulhu $[[R2:[0-9]+]], 4($[[R1]])
; CHECK-EB: sll $[[R4:[0-9]+]], $[[R2]], 16
; CHECK-EB: or $5, $[[R4]], $[[R5]]
; CHECK-EB: ulw $4, 0($[[R1]])
; CHECK-EB: lw $25, %call16(foo4)
; CHECK-EB: or $5, $[[R4]], $[[R5]]
tail call void @foo2(%struct.S1* byval getelementptr inbounds (%struct.S2* @s2, i32 0, i32 1)) nounwind
tail call void @foo4(%struct.S4* byval @s4) nounwind

12
test/CodeGen/PTX/cvt.ll
View File

@ -172,9 +172,9 @@ define ptx_device i64 @cvt_i64_f64(double %x) {
; f32
define ptx_device float @cvt_f32_preds(i1 %x) {
; CHECK: mov.b32 %f0, 1065353216;
; CHECK: mov.b32 %f1, 0;
; CHECK: selp.f32 %ret{{[0-9]+}}, %f0, %f1, %p{{[0-9]+}};
; CHECK: mov.b32 %f0, 0;
; CHECK: mov.b32 %f1, 1065353216;
; CHECK: selp.f32 %ret{{[0-9]+}}, %f1, %f0, %p{{[0-9]+}};
; CHECK: ret;
%a = uitofp i1 %x to float
ret float %a
@ -232,9 +232,9 @@ define ptx_device float @cvt_f32_s64(i64 %x) {
; f64
define ptx_device double @cvt_f64_preds(i1 %x) {
; CHECK: mov.b64 %fd0, 4575657221408423936;
; CHECK: mov.b64 %fd1, 0;
; CHECK: selp.f64 %ret{{[0-9]+}}, %fd0, %fd1, %p{{[0-9]+}};
; CHECK: mov.b64 %fd0, 0;
; CHECK: mov.b64 %fd1, 4575657221408423936;
; CHECK: selp.f64 %ret{{[0-9]+}}, %fd1, %fd0, %p{{[0-9]+}};
; CHECK: ret;
%a = uitofp i1 %x to double
ret double %a

23
test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll
View File

@ -1,23 +0,0 @@
; RUN: llc < %s -march=ppc32 -combiner-alias-analysis | grep f5
target datalayout = "E-p:32:32"
target triple = "powerpc-apple-darwin8.2.0"
%struct.Point = type { double, double, double }
define void @offset(%struct.Point* %pt, double %x, double %y, double %z) {
entry:
%tmp = getelementptr %struct.Point* %pt, i32 0, i32 0 ; <double*> [#uses=2]
%tmp.upgrd.1 = load double* %tmp ; <double> [#uses=1]
%tmp2 = fadd double %tmp.upgrd.1, %x ; <double> [#uses=1]
store double %tmp2, double* %tmp
%tmp6 = getelementptr %struct.Point* %pt, i32 0, i32 1 ; <double*> [#uses=2]
%tmp7 = load double* %tmp6 ; <double> [#uses=1]
%tmp9 = fadd double %tmp7, %y ; <double> [#uses=1]
store double %tmp9, double* %tmp6
%tmp13 = getelementptr %struct.Point* %pt, i32 0, i32 2 ; <double*> [#uses=2]
%tmp14 = load double* %tmp13 ; <double> [#uses=1]
%tmp16 = fadd double %tmp14, %z ; <double> [#uses=1]
store double %tmp16, double* %tmp13
ret void
}

6
test/CodeGen/PowerPC/LargeAbsoluteAddr.ll
View File

@ -1,9 +1,9 @@
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin | \
; RUN: grep {stw r3, 32751}
; RUN: grep {stw r4, 32751}
; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \
; RUN: grep {stw r3, 32751}
; RUN: grep {stw r4, 32751}
; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \
; RUN: grep {std r3, 9024}
; RUN: grep {std r4, 9024}
define void @test() nounwind {
store i32 0, i32* inttoptr (i64 48725999 to i32*)

2
test/CodeGen/PowerPC/indirectbr.ll
View File

@ -47,8 +47,8 @@ L2: ; preds = %L3, %bb2
L1: ; preds = %L2, %bb2
%res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ] ; <i32> [#uses=1]
; PIC: addis r[[R0:[0-9]+]], r{{[0-9]+}}, ha16(Ltmp0-L0$pb)
; PIC: li r[[R1:[0-9]+]], lo16(Ltmp0-L0$pb)
; PIC: addis r[[R0:[0-9]+]], r{{[0-9]+}}, ha16(Ltmp0-L0$pb)
; PIC: add r[[R2:[0-9]+]], r[[R0]], r[[R1]]
; PIC: stw r[[R2]]
; STATIC: li r[[R0:[0-9]+]], lo16(Ltmp0)

197
test/CodeGen/PowerPC/ppc32-vaarg.ll
View File

@ -12,156 +12,151 @@ target triple = "powerpc-unknown-freebsd9.0"
define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind {
entry:
%x = va_arg %struct.__va_list_tag* %ap, i64; Get from r5,r6
; CHECK: lbz 4, 0(3)
; CHECK-NEXT: lwz 5, 4(3)
; CHECK-NEXT: rlwinm 6, 4, 0, 31, 31
; CHECK-NEXT: cmplwi 0, 6, 0
; CHECK-NEXT: addi 6, 4, 1
; CHECK: lbz 4, 0(3)
; CHECK-NEXT: rlwinm 5, 4, 0, 31, 31
; CHECK-NEXT: cmplwi 0, 5, 0
; CHECK-NEXT: addi 5, 4, 1
; CHECK-NEXT: stw 3, -4(1)
; CHECK-NEXT: stw 6, -8(1)
; CHECK-NEXT: stw 5, -8(1)
; CHECK-NEXT: stw 4, -12(1)
; CHECK-NEXT: stw 5, -16(1)
; CHECK-NEXT: bne 0, .LBB0_2
; CHECK-NEXT: # BB#1: # %entry
; CHECK-NEXT: lwz 3, -12(1)
; CHECK-NEXT: stw 3, -8(1)
; CHECK-NEXT: .LBB0_2: # %entry
; CHECK-NEXT: lwz 3, -8(1)
; CHECK-NEXT: lwz 4, -4(1)
; CHECK-NEXT: lwz 5, 8(4)
; CHECK-NEXT: slwi 6, 3, 2
; CHECK-NEXT: addi 7, 3, 2
; CHECK-NEXT: slwi 4, 3, 2
; CHECK-NEXT: lwz 5, -4(1)
; CHECK-NEXT: lwz 6, 4(5)
; CHECK-NEXT: lwz 7, 8(5)
; CHECK-NEXT: add 4, 7, 4
; CHECK-NEXT: cmpwi 0, 3, 8
; CHECK-NEXT: lwz 3, -16(1)
; CHECK-NEXT: addi 8, 3, 4
; CHECK-NEXT: add 5, 5, 6
; CHECK-NEXT: mfcr 0 # cr0
; CHECK-NEXT: stw 0, -20(1)
; CHECK-NEXT: stw 5, -24(1)
; CHECK-NEXT: stw 3, -28(1)
; CHECK-NEXT: stw 7, -32(1)
; CHECK-NEXT: stw 8, -36(1)
; CHECK-NEXT: stw 0, -16(1)
; CHECK-NEXT: stw 3, -20(1)
; CHECK-NEXT: stw 4, -24(1)
; CHECK-NEXT: stw 6, -28(1)
; CHECK-NEXT: blt 0, .LBB0_4
; CHECK-NEXT: # BB#3: # %entry
; CHECK-NEXT: lwz 3, -36(1)
; CHECK-NEXT: stw 3, -28(1)
; CHECK-NEXT: .LBB0_4: # %entry
; CHECK-NEXT: lwz 3, -28(1)
; CHECK-NEXT: lwz 4, -32(1)
; CHECK-NEXT: lwz 5, -4(1)
; CHECK-NEXT: stb 4, 0(5)
; CHECK-NEXT: lwz 4, -24(1)
; CHECK-NEXT: lwz 0, -20(1)
; CHECK-NEXT: stw 3, -24(1)
; CHECK-NEXT: .LBB0_4: # %entry
; CHECK-NEXT: lwz 3, -24(1)
; CHECK-NEXT: lwz 4, -28(1)
; CHECK-NEXT: addi 5, 4, 4
; CHECK-NEXT: lwz 0, -16(1)
; CHECK-NEXT: mtcrf 128, 0
; CHECK-NEXT: stw 4, -32(1)
; CHECK-NEXT: stw 5, -36(1)
; CHECK-NEXT: stw 3, -40(1)
; CHECK-NEXT: stw 4, -44(1)
; CHECK-NEXT: blt 0, .LBB0_6
; CHECK-NEXT: # BB#5: # %entry
; CHECK-NEXT: lwz 3, -16(1)
; CHECK-NEXT: stw 3, -44(1)
; CHECK-NEXT: lwz 3, -36(1)
; CHECK-NEXT: stw 3, -32(1)
; CHECK-NEXT: .LBB0_6: # %entry
; CHECK-NEXT: lwz 3, -44(1)
; CHECK-NEXT: lwz 4, -40(1)
; CHECK-NEXT: lwz 5, -4(1)
; CHECK-NEXT: stw 4, 4(5)
; CHECK-NEXT: lwz 3, -32(1)
; CHECK-NEXT: lwz 4, -20(1)
; CHECK-NEXT: addi 5, 4, 2
; CHECK-NEXT: lwz 6, -4(1)
; CHECK-NEXT: stb 5, 0(6)
; CHECK-NEXT: stw 3, 4(6)
store i64 %x, i64* @var1, align 8
; CHECK-NEXT: lis 4, var1@ha
; CHECK-NEXT: lwz 6, 4(3)
; CHECK-NEXT: lwz 3, 0(3)
; CHECK-NEXT: la 7, var1@l(4)
; CHECK-NEXT: stw 3, var1@l(4)
; CHECK-NEXT: stw 6, 4(7)
; CHECK-NEXT: lwz 3, -40(1)
; CHECK-NEXT: lwz 5, 0(3)
; CHECK-NEXT: lwz 7, 4(3)
; CHECK-NEXT: lis 8, var1@ha
; CHECK-NEXT: la 9, var1@l(8)
; CHECK-NEXT: stw 7, 4(9)
; CHECK-NEXT: stw 5, var1@l(8)
%y = va_arg %struct.__va_list_tag* %ap, double; From f1
; CHECK-NEXT: lbz 3, 1(5)
; CHECK-NEXT: lwz 4, 4(5)
; CHECK-NEXT: lwz 6, 8(5)
; CHECK-NEXT: slwi 7, 3, 3
; CHECK-NEXT: add 6, 6, 7
; CHECK-NEXT: addi 7, 3, 1
; CHECK-NEXT: cmpwi 0, 3, 8
; CHECK-NEXT: addi 3, 4, 8
; CHECK-NEXT: addi 6, 6, 32
; CHECK-NEXT: mr 8, 4
; CHECK-NEXT: lbz 5, 1(6)
; CHECK-NEXT: lwz 7, 4(6)
; CHECK-NEXT: lwz 8, 8(6)
; CHECK-NEXT: slwi 9, 5, 3
; CHECK-NEXT: add 8, 8, 9
; CHECK-NEXT: cmpwi 0, 5, 8
; CHECK-NEXT: addi 9, 7, 8
; CHECK-NEXT: mr 10, 7
; CHECK-NEXT: stw 9, -44(1)
; CHECK-NEXT: stw 7, -48(1)
; CHECK-NEXT: mfcr 0 # cr0
; CHECK-NEXT: stw 0, -48(1)
; CHECK-NEXT: stw 4, -52(1)
; CHECK-NEXT: stw 6, -56(1)
; CHECK-NEXT: stw 7, -60(1)
; CHECK-NEXT: stw 3, -64(1)
; CHECK-NEXT: stw 8, -68(1)
; CHECK-NEXT: stw 0, -52(1)
; CHECK-NEXT: stw 5, -56(1)
; CHECK-NEXT: stw 10, -60(1)
; CHECK-NEXT: stw 8, -64(1)
; CHECK-NEXT: blt 0, .LBB0_8
; CHECK-NEXT: # BB#7: # %entry
; CHECK-NEXT: lwz 3, -64(1)
; CHECK-NEXT: stw 3, -68(1)
; CHECK-NEXT: lwz 3, -44(1)
; CHECK-NEXT: stw 3, -60(1)
; CHECK-NEXT: .LBB0_8: # %entry
; CHECK-NEXT: lwz 3, -68(1)
; CHECK-NEXT: lwz 4, -60(1)
; CHECK-NEXT: lwz 5, -4(1)
; CHECK-NEXT: stb 4, 1(5)
; CHECK-NEXT: lwz 4, -56(1)
; CHECK-NEXT: lwz 0, -48(1)
; CHECK-NEXT: lwz 3, -60(1)
; CHECK-NEXT: lwz 4, -64(1)
; CHECK-NEXT: addi 4, 4, 32
; CHECK-NEXT: lwz 0, -52(1)
; CHECK-NEXT: mtcrf 128, 0
; CHECK-NEXT: stw 4, -72(1)
; CHECK-NEXT: stw 3, -76(1)
; CHECK-NEXT: stw 4, -68(1)
; CHECK-NEXT: stw 3, -72(1)
; CHECK-NEXT: blt 0, .LBB0_10
; CHECK-NEXT: # BB#9: # %entry
; CHECK-NEXT: lwz 3, -52(1)
; CHECK-NEXT: stw 3, -72(1)
; CHECK-NEXT: lwz 3, -48(1)
; CHECK-NEXT: stw 3, -68(1)
; CHECK-NEXT: .LBB0_10: # %entry
; CHECK-NEXT: lwz 3, -72(1)
; CHECK-NEXT: lwz 4, -76(1)
; CHECK-NEXT: lwz 5, -4(1)
; CHECK-NEXT: stw 4, 4(5)
; CHECK-NEXT: lwz 3, -68(1)
; CHECK-NEXT: lwz 4, -56(1)
; CHECK-NEXT: addi 5, 4, 1
; CHECK-NEXT: lwz 6, -4(1)
; CHECK-NEXT: stb 5, 1(6)
; CHECK-NEXT: lwz 5, -72(1)
; CHECK-NEXT: stw 5, 4(6)
; CHECK-NEXT: lfd 0, 0(3)
store double %y, double* @var2, align 8
; CHECK-NEXT: lis 3, var2@ha
; CHECK-NEXT: stfd 0, var2@l(3)
%z = va_arg %struct.__va_list_tag* %ap, i32; From r7
; CHECK-NEXT: lbz 3, 0(5)
; CHECK-NEXT: lwz 4, 4(5)
; CHECK-NEXT: lwz 6, 8(5)
; CHECK-NEXT: slwi 7, 3, 2
; CHECK-NEXT: addi 8, 3, 1
; CHECK-NEXT: lbz 3, 0(6)
; CHECK-NEXT: lwz 5, 4(6)
; CHECK-NEXT: lwz 7, 8(6)
; CHECK-NEXT: slwi 8, 3, 2
; CHECK-NEXT: add 7, 7, 8
; CHECK-NEXT: cmpwi 0, 3, 8
; CHECK-NEXT: addi 3, 4, 4
; CHECK-NEXT: add 6, 6, 7
; CHECK-NEXT: mr 7, 4
; CHECK-NEXT: stw 6, -80(1)
; CHECK-NEXT: addi 8, 5, 4
; CHECK-NEXT: mr 9, 5
; CHECK-NEXT: stw 3, -76(1)
; CHECK-NEXT: stw 7, -80(1)
; CHECK-NEXT: stw 8, -84(1)
; CHECK-NEXT: stw 3, -88(1)
; CHECK-NEXT: stw 4, -92(1)
; CHECK-NEXT: stw 7, -96(1)
; CHECK-NEXT: stw 5, -88(1)
; CHECK-NEXT: stw 9, -92(1)
; CHECK-NEXT: mfcr 0 # cr0
; CHECK-NEXT: stw 0, -100(1)
; CHECK-NEXT: stw 0, -96(1)
; CHECK-NEXT: blt 0, .LBB0_12
; CHECK-NEXT: # BB#11: # %entry
; CHECK-NEXT: lwz 3, -88(1)
; CHECK-NEXT: stw 3, -96(1)
; CHECK-NEXT: lwz 3, -84(1)
; CHECK-NEXT: stw 3, -92(1)
; CHECK-NEXT: .LBB0_12: # %entry
; CHECK-NEXT: lwz 3, -96(1)
; CHECK-NEXT: lwz 4, -84(1)
; CHECK-NEXT: lwz 5, -4(1)
; CHECK-NEXT: stb 4, 0(5)
; CHECK-NEXT: lwz 3, -92(1)
; CHECK-NEXT: lwz 4, -80(1)
; CHECK-NEXT: lwz 0, -100(1)
; CHECK-NEXT: lwz 0, -96(1)
; CHECK-NEXT: mtcrf 128, 0
; CHECK-NEXT: stw 3, -100(1)
; CHECK-NEXT: stw 4, -104(1)
; CHECK-NEXT: stw 3, -108(1)
; CHECK-NEXT: blt 0, .LBB0_14
; CHECK-NEXT: # BB#13: # %entry
; CHECK-NEXT: lwz 3, -92(1)
; CHECK-NEXT: lwz 3, -88(1)
; CHECK-NEXT: stw 3, -104(1)
; CHECK-NEXT: .LBB0_14: # %entry
; CHECK-NEXT: lwz 3, -104(1)
; CHECK-NEXT: lwz 4, -108(1)
; CHECK-NEXT: lwz 5, -4(1)
; CHECK-NEXT: stw 4, 4(5)
; CHECK-NEXT: lwz 4, -76(1)
; CHECK-NEXT: addi 5, 4, 1
; CHECK-NEXT: lwz 6, -4(1)
; CHECK-NEXT: stb 5, 0(6)
; CHECK-NEXT: lwz 5, -100(1)
; CHECK-NEXT: stw 5, 4(6)
; CHECK-NEXT: lwz 3, 0(3)
store i32 %z, i32* @var3, align 4
; CHECK-NEXT: lis 4, var3@ha
; CHECK-NEXT: stw 3, var3@l(4)
; CHECK-NEXT: lis 5, var3@ha
; CHECK-NEXT: stw 3, var3@l(5)
ret void
; CHECK-NEXT: stw 5, -112(1)
; CHECK-NEXT: blr
; CHECK-NEXT: stw 6, -108(1)
; CHECK-NEXT: blr
}