mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-19 23:29:20 +00:00
Reindent code, improve comments, move huge nested methods out of classes,
prune #includes, add print/dump methods, etc. No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16604 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
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lib/CodeGen
@ -7,353 +7,367 @@
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//
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//
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// This file implements the virtual register map. It also implements
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// This file implements the VirtRegMap class.
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// the eliminateVirtRegs() function that given a virtual register map
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//
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// and a machine function it eliminates all virtual references by
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// It also contains implementations of the the Spiller interface, which, given a
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// replacing them with physical register references and adds spill
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// virtual register map and a machine function, eliminates all virtual
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// references by replacing them with physical register references - adding spill
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// code as necessary.
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// code as necessary.
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#define DEBUG_TYPE "spiller"
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#include "VirtRegMap.h"
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#include "VirtRegMap.h"
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#include "llvm/Function.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/STLExtras.h"
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using namespace llvm;
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using namespace llvm;
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namespace {
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namespace {
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Statistic<> numSpills("spiller", "Number of register spills");
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Statistic<> NumSpills("spiller", "Number of register spills");
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Statistic<> numStores("spiller", "Number of stores added");
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Statistic<> NumStores("spiller", "Number of stores added");
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Statistic<> numLoads ("spiller", "Number of loads added");
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Statistic<> NumLoads ("spiller", "Number of loads added");
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enum SpillerName { simple, local };
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enum SpillerName { simple, local };
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cl::opt<SpillerName>
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cl::opt<SpillerName>
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SpillerOpt("spiller",
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SpillerOpt("spiller",
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cl::desc("Spiller to use: (default: local)"),
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cl::desc("Spiller to use: (default: local)"),
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cl::Prefix,
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cl::Prefix,
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cl::values(clEnumVal(simple, " simple spiller"),
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cl::values(clEnumVal(simple, " simple spiller"),
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clEnumVal(local, " local spiller"),
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clEnumVal(local, " local spiller"),
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clEnumValEnd),
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clEnumValEnd),
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cl::init(local));
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cl::init(local));
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}
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}
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int VirtRegMap::assignVirt2StackSlot(unsigned virtReg)
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//===----------------------------------------------------------------------===//
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{
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// VirtRegMap implementation
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assert(MRegisterInfo::isVirtualRegister(virtReg));
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//===----------------------------------------------------------------------===//
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assert(v2ssMap_[virtReg] == NO_STACK_SLOT &&
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"attempt to assign stack slot to already spilled register");
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void VirtRegMap::grow() {
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const TargetRegisterClass* RC =
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v2pMap_.grow(mf_->getSSARegMap()->getLastVirtReg());
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mf_->getSSARegMap()->getRegClass(virtReg);
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v2ssMap_.grow(mf_->getSSARegMap()->getLastVirtReg());
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int frameIndex = mf_->getFrameInfo()->CreateStackObject(RC->getSize(),
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RC->getAlignment());
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v2ssMap_[virtReg] = frameIndex;
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++numSpills;
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return frameIndex;
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}
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}
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void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex)
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int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
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{
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assert(MRegisterInfo::isVirtualRegister(virtReg));
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assert(MRegisterInfo::isVirtualRegister(virtReg));
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assert(v2ssMap_[virtReg] == NO_STACK_SLOT &&
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assert(v2ssMap_[virtReg] == NO_STACK_SLOT &&
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"attempt to assign stack slot to already spilled register");
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"attempt to assign stack slot to already spilled register");
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const TargetRegisterClass* RC = mf_->getSSARegMap()->getRegClass(virtReg);
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v2ssMap_[virtReg] = frameIndex;
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int frameIndex = mf_->getFrameInfo()->CreateStackObject(RC->getSize(),
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RC->getAlignment());
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v2ssMap_[virtReg] = frameIndex;
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++NumSpills;
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return frameIndex;
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}
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void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
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assert(MRegisterInfo::isVirtualRegister(virtReg));
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assert(v2ssMap_[virtReg] == NO_STACK_SLOT &&
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"attempt to assign stack slot to already spilled register");
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v2ssMap_[virtReg] = frameIndex;
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}
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}
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void VirtRegMap::virtFolded(unsigned virtReg,
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void VirtRegMap::virtFolded(unsigned virtReg,
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MachineInstr* oldMI,
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MachineInstr* oldMI,
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MachineInstr* newMI)
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MachineInstr* newMI) {
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{
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// move previous memory references folded to new instruction
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// move previous memory references folded to new instruction
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MI2VirtMap::iterator i, e;
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MI2VirtMap::iterator i, e;
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std::vector<MI2VirtMap::mapped_type> regs;
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std::vector<MI2VirtMap::mapped_type> regs;
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for (tie(i, e) = mi2vMap_.equal_range(oldMI); i != e; ) {
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for (tie(i, e) = mi2vMap_.equal_range(oldMI); i != e; ) {
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regs.push_back(i->second);
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regs.push_back(i->second);
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mi2vMap_.erase(i++);
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mi2vMap_.erase(i++);
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}
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}
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for (unsigned i = 0, e = regs.size(); i != e; ++i)
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for (unsigned i = 0, e = regs.size(); i != e; ++i)
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mi2vMap_.insert(std::make_pair(newMI, i));
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mi2vMap_.insert(std::make_pair(newMI, i));
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// add new memory reference
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// add new memory reference
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mi2vMap_.insert(std::make_pair(newMI, virtReg));
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mi2vMap_.insert(std::make_pair(newMI, virtReg));
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}
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}
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std::ostream& llvm::operator<<(std::ostream& os, const VirtRegMap& vrm)
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void VirtRegMap::print(std::ostream& os) const {
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{
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const MRegisterInfo* mri = mf_->getTarget().getRegisterInfo();
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const MRegisterInfo* mri = vrm.mf_->getTarget().getRegisterInfo();
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std::cerr << "********** REGISTER MAP **********\n";
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std::cerr << "********** REGISTER MAP **********\n";
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for (unsigned i = MRegisterInfo::FirstVirtualRegister,
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for (unsigned i = MRegisterInfo::FirstVirtualRegister,
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e = vrm.mf_->getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
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e = mf_->getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
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if (vrm.v2pMap_[i] != VirtRegMap::NO_PHYS_REG)
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if (v2pMap_[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
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std::cerr << "[reg" << i << " -> "
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std::cerr << "[reg" << i << " -> "
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<< mri->getName(vrm.v2pMap_[i]) << "]\n";
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<< mri->getName(v2pMap_[i]) << "]\n";
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}
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}
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for (unsigned i = MRegisterInfo::FirstVirtualRegister,
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e = vrm.mf_->getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
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for (unsigned i = MRegisterInfo::FirstVirtualRegister,
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if (vrm.v2ssMap_[i] != VirtRegMap::NO_STACK_SLOT)
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e = mf_->getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
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std::cerr << "[reg" << i << " -> fi#"
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if (v2ssMap_[i] != VirtRegMap::NO_STACK_SLOT)
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<< vrm.v2ssMap_[i] << "]\n";
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std::cerr << "[reg" << i << " -> fi#"
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}
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<< v2ssMap_[i] << "]\n";
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return std::cerr << '\n';
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}
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std::cerr << '\n';
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}
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}
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Spiller::~Spiller()
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void VirtRegMap::dump() const { print(std::cerr); }
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{
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}
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//===----------------------------------------------------------------------===//
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// Simple Spiller Implementation
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//===----------------------------------------------------------------------===//
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Spiller::~Spiller() {}
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namespace {
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namespace {
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struct SimpleSpiller : public Spiller {
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class SimpleSpiller : public Spiller {
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bool runOnMachineFunction(MachineFunction& mf, const VirtRegMap &VRM);
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public:
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};
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bool runOnMachineFunction(MachineFunction& mf, const VirtRegMap& vrm) {
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DEBUG(std::cerr << "********** REWRITE MACHINE CODE **********\n");
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DEBUG(std::cerr << "********** Function: "
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<< mf.getFunction()->getName() << '\n');
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const TargetMachine& tm = mf.getTarget();
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const MRegisterInfo& mri = *tm.getRegisterInfo();
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typedef DenseMap<bool, VirtReg2IndexFunctor> Loaded;
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Loaded loaded;
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for (MachineFunction::iterator mbbi = mf.begin(),
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mbbe = mf.end(); mbbi != mbbe; ++mbbi) {
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DEBUG(std::cerr << mbbi->getBasicBlock()->getName() << ":\n");
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for (MachineBasicBlock::iterator mii = mbbi->begin(),
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mie = mbbi->end(); mii != mie; ++mii) {
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loaded.grow(mf.getSSARegMap()->getLastVirtReg());
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for (unsigned i = 0,e = mii->getNumOperands(); i != e; ++i){
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MachineOperand& mop = mii->getOperand(i);
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if (mop.isRegister() && mop.getReg() &&
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MRegisterInfo::isVirtualRegister(mop.getReg())) {
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unsigned virtReg = mop.getReg();
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unsigned physReg = vrm.getPhys(virtReg);
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if (mop.isUse() &&
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vrm.hasStackSlot(mop.getReg()) &&
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!loaded[virtReg]) {
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mri.loadRegFromStackSlot(
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*mbbi,
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mii,
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physReg,
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vrm.getStackSlot(virtReg));
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loaded[virtReg] = true;
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DEBUG(std::cerr << '\t';
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prior(mii)->print(std::cerr, &tm));
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++numLoads;
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}
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if (mop.isDef() &&
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vrm.hasStackSlot(mop.getReg())) {
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mri.storeRegToStackSlot(
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*mbbi,
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next(mii),
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physReg,
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vrm.getStackSlot(virtReg));
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++numStores;
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}
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mii->SetMachineOperandReg(i, physReg);
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}
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}
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DEBUG(std::cerr << '\t'; mii->print(std::cerr, &tm));
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loaded.clear();
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}
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}
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return true;
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}
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};
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class LocalSpiller : public Spiller {
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typedef std::vector<unsigned> Phys2VirtMap;
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typedef std::vector<bool> PhysFlag;
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typedef DenseMap<MachineInstr*, VirtReg2IndexFunctor> Virt2MI;
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MachineFunction* mf_;
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const TargetMachine* tm_;
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const TargetInstrInfo* tii_;
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const MRegisterInfo* mri_;
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const VirtRegMap* vrm_;
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Phys2VirtMap p2vMap_;
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PhysFlag dirty_;
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Virt2MI lastDef_;
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public:
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bool runOnMachineFunction(MachineFunction& mf, const VirtRegMap& vrm) {
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mf_ = &mf;
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tm_ = &mf_->getTarget();
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tii_ = tm_->getInstrInfo();
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mri_ = tm_->getRegisterInfo();
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vrm_ = &vrm;
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p2vMap_.assign(mri_->getNumRegs(), 0);
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dirty_.assign(mri_->getNumRegs(), false);
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DEBUG(std::cerr << "********** REWRITE MACHINE CODE **********\n");
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DEBUG(std::cerr << "********** Function: "
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<< mf_->getFunction()->getName() << '\n');
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for (MachineFunction::iterator mbbi = mf_->begin(),
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mbbe = mf_->end(); mbbi != mbbe; ++mbbi) {
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lastDef_.grow(mf_->getSSARegMap()->getLastVirtReg());
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DEBUG(std::cerr << mbbi->getBasicBlock()->getName() << ":\n");
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eliminateVirtRegsInMbb(*mbbi);
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// clear map, dirty flag and last ref
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p2vMap_.assign(p2vMap_.size(), 0);
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dirty_.assign(dirty_.size(), false);
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lastDef_.clear();
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}
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return true;
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}
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private:
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void vacateJustPhysReg(MachineBasicBlock& mbb,
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MachineBasicBlock::iterator mii,
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unsigned physReg) {
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unsigned virtReg = p2vMap_[physReg];
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if (dirty_[physReg] && vrm_->hasStackSlot(virtReg)) {
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assert(lastDef_[virtReg] && "virtual register is mapped "
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"to a register and but was not defined!");
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MachineBasicBlock::iterator lastDef = lastDef_[virtReg];
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MachineBasicBlock::iterator nextLastRef = next(lastDef);
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mri_->storeRegToStackSlot(*lastDef->getParent(),
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nextLastRef,
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physReg,
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vrm_->getStackSlot(virtReg));
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++numStores;
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DEBUG(std::cerr << "added: ";
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prior(nextLastRef)->print(std::cerr, tm_);
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std::cerr << "after: ";
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lastDef->print(std::cerr, tm_));
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lastDef_[virtReg] = 0;
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}
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p2vMap_[physReg] = 0;
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dirty_[physReg] = false;
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}
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void vacatePhysReg(MachineBasicBlock& mbb,
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MachineBasicBlock::iterator mii,
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unsigned physReg) {
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vacateJustPhysReg(mbb, mii, physReg);
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for (const unsigned* as = mri_->getAliasSet(physReg); *as; ++as)
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vacateJustPhysReg(mbb, mii, *as);
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}
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void handleUse(MachineBasicBlock& mbb,
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MachineBasicBlock::iterator mii,
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unsigned virtReg,
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unsigned physReg) {
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// check if we are replacing a previous mapping
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if (p2vMap_[physReg] != virtReg) {
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vacatePhysReg(mbb, mii, physReg);
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p2vMap_[physReg] = virtReg;
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// load if necessary
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if (vrm_->hasStackSlot(virtReg)) {
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mri_->loadRegFromStackSlot(mbb, mii, physReg,
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vrm_->getStackSlot(virtReg));
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++numLoads;
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DEBUG(std::cerr << "added: ";
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prior(mii)->print(std::cerr, tm_));
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lastDef_[virtReg] = mii;
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}
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}
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}
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void handleDef(MachineBasicBlock& mbb,
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MachineBasicBlock::iterator mii,
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unsigned virtReg,
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unsigned physReg) {
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// check if we are replacing a previous mapping
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if (p2vMap_[physReg] != virtReg)
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vacatePhysReg(mbb, mii, physReg);
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p2vMap_[physReg] = virtReg;
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dirty_[physReg] = true;
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lastDef_[virtReg] = mii;
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}
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void eliminateVirtRegsInMbb(MachineBasicBlock& mbb) {
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for (MachineBasicBlock::iterator mii = mbb.begin(),
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mie = mbb.end(); mii != mie; ++mii) {
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// if we have references to memory operands make sure
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// we clear all physical registers that may contain
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// the value of the spilled virtual register
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VirtRegMap::MI2VirtMap::const_iterator i, e;
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for (tie(i, e) = vrm_->getFoldedVirts(mii); i != e; ++i) {
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if (vrm_->hasPhys(i->second))
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vacateJustPhysReg(mbb, mii, vrm_->getPhys(i->second));
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}
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// rewrite all used operands
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for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
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MachineOperand& op = mii->getOperand(i);
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if (op.isRegister() && op.getReg() && op.isUse() &&
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|
||||||
MRegisterInfo::isVirtualRegister(op.getReg())) {
|
|
||||||
unsigned virtReg = op.getReg();
|
|
||||||
unsigned physReg = vrm_->getPhys(virtReg);
|
|
||||||
handleUse(mbb, mii, virtReg, physReg);
|
|
||||||
mii->SetMachineOperandReg(i, physReg);
|
|
||||||
// mark as dirty if this is def&use
|
|
||||||
if (op.isDef()) {
|
|
||||||
dirty_[physReg] = true;
|
|
||||||
lastDef_[virtReg] = mii;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
// spill implicit physical register defs
|
|
||||||
const TargetInstrDescriptor& tid = tii_->get(mii->getOpcode());
|
|
||||||
for (const unsigned* id = tid.ImplicitDefs; *id; ++id)
|
|
||||||
vacatePhysReg(mbb, mii, *id);
|
|
||||||
|
|
||||||
// spill explicit physical register defs
|
|
||||||
for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
|
|
||||||
MachineOperand& op = mii->getOperand(i);
|
|
||||||
if (op.isRegister() && op.getReg() && !op.isUse() &&
|
|
||||||
MRegisterInfo::isPhysicalRegister(op.getReg()))
|
|
||||||
vacatePhysReg(mbb, mii, op.getReg());
|
|
||||||
}
|
|
||||||
|
|
||||||
// rewrite def operands (def&use was handled with the
|
|
||||||
// uses so don't check for those here)
|
|
||||||
for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
|
|
||||||
MachineOperand& op = mii->getOperand(i);
|
|
||||||
if (op.isRegister() && op.getReg() && !op.isUse())
|
|
||||||
if (MRegisterInfo::isPhysicalRegister(op.getReg()))
|
|
||||||
vacatePhysReg(mbb, mii, op.getReg());
|
|
||||||
else {
|
|
||||||
unsigned physReg = vrm_->getPhys(op.getReg());
|
|
||||||
handleDef(mbb, mii, op.getReg(), physReg);
|
|
||||||
mii->SetMachineOperandReg(i, physReg);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
DEBUG(std::cerr << '\t'; mii->print(std::cerr, tm_));
|
|
||||||
}
|
|
||||||
|
|
||||||
for (unsigned i = 1, e = p2vMap_.size(); i != e; ++i)
|
|
||||||
vacateJustPhysReg(mbb, mbb.getFirstTerminator(), i);
|
|
||||||
|
|
||||||
}
|
|
||||||
};
|
|
||||||
}
|
}
|
||||||
|
|
||||||
llvm::Spiller* llvm::createSpiller()
|
bool SimpleSpiller::runOnMachineFunction(MachineFunction& MF,
|
||||||
{
|
const VirtRegMap& VRM) {
|
||||||
switch (SpillerOpt) {
|
DEBUG(std::cerr << "********** REWRITE MACHINE CODE **********\n");
|
||||||
default:
|
DEBUG(std::cerr << "********** Function: "
|
||||||
std::cerr << "no spiller selected";
|
<< MF.getFunction()->getName() << '\n');
|
||||||
abort();
|
const TargetMachine& TM = MF.getTarget();
|
||||||
case local:
|
const MRegisterInfo& mri = *TM.getRegisterInfo();
|
||||||
return new LocalSpiller();
|
|
||||||
case simple:
|
DenseMap<bool, VirtReg2IndexFunctor> Loaded;
|
||||||
return new SimpleSpiller();
|
|
||||||
|
for (MachineFunction::iterator mbbi = MF.begin(), E = MF.end();
|
||||||
|
mbbi != E; ++mbbi) {
|
||||||
|
DEBUG(std::cerr << mbbi->getBasicBlock()->getName() << ":\n");
|
||||||
|
for (MachineBasicBlock::iterator mii = mbbi->begin(),
|
||||||
|
mie = mbbi->end(); mii != mie; ++mii) {
|
||||||
|
Loaded.grow(MF.getSSARegMap()->getLastVirtReg());
|
||||||
|
for (unsigned i = 0,e = mii->getNumOperands(); i != e; ++i){
|
||||||
|
MachineOperand& mop = mii->getOperand(i);
|
||||||
|
if (mop.isRegister() && mop.getReg() &&
|
||||||
|
MRegisterInfo::isVirtualRegister(mop.getReg())) {
|
||||||
|
unsigned virtReg = mop.getReg();
|
||||||
|
unsigned physReg = VRM.getPhys(virtReg);
|
||||||
|
if (mop.isUse() && VRM.hasStackSlot(mop.getReg()) &&
|
||||||
|
!Loaded[virtReg]) {
|
||||||
|
mri.loadRegFromStackSlot(*mbbi, mii, physReg,
|
||||||
|
VRM.getStackSlot(virtReg));
|
||||||
|
Loaded[virtReg] = true;
|
||||||
|
DEBUG(std::cerr << '\t';
|
||||||
|
prior(mii)->print(std::cerr, &TM));
|
||||||
|
++NumLoads;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (mop.isDef() && VRM.hasStackSlot(mop.getReg())) {
|
||||||
|
mri.storeRegToStackSlot(*mbbi, next(mii), physReg,
|
||||||
|
VRM.getStackSlot(virtReg));
|
||||||
|
++NumStores;
|
||||||
|
}
|
||||||
|
mii->SetMachineOperandReg(i, physReg);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
DEBUG(std::cerr << '\t'; mii->print(std::cerr, &TM));
|
||||||
|
Loaded.clear();
|
||||||
}
|
}
|
||||||
|
}
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
//===----------------------------------------------------------------------===//
|
||||||
|
// Local Spiller Implementation
|
||||||
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
|
namespace {
|
||||||
|
class LocalSpiller : public Spiller {
|
||||||
|
typedef std::vector<unsigned> Phys2VirtMap;
|
||||||
|
typedef std::vector<bool> PhysFlag;
|
||||||
|
typedef DenseMap<MachineInstr*, VirtReg2IndexFunctor> Virt2MI;
|
||||||
|
|
||||||
|
MachineFunction *MF;
|
||||||
|
const TargetMachine *TM;
|
||||||
|
const TargetInstrInfo *TII;
|
||||||
|
const MRegisterInfo *MRI;
|
||||||
|
const VirtRegMap *VRM;
|
||||||
|
Phys2VirtMap p2vMap_;
|
||||||
|
PhysFlag dirty_;
|
||||||
|
Virt2MI lastDef_;
|
||||||
|
|
||||||
|
public:
|
||||||
|
bool runOnMachineFunction(MachineFunction &MF, const VirtRegMap &VRM);
|
||||||
|
|
||||||
|
private:
|
||||||
|
void vacateJustPhysReg(MachineBasicBlock& mbb,
|
||||||
|
MachineBasicBlock::iterator mii,
|
||||||
|
unsigned physReg);
|
||||||
|
|
||||||
|
void vacatePhysReg(MachineBasicBlock& mbb,
|
||||||
|
MachineBasicBlock::iterator mii,
|
||||||
|
unsigned physReg) {
|
||||||
|
vacateJustPhysReg(mbb, mii, physReg);
|
||||||
|
for (const unsigned* as = MRI->getAliasSet(physReg); *as; ++as)
|
||||||
|
vacateJustPhysReg(mbb, mii, *as);
|
||||||
|
}
|
||||||
|
|
||||||
|
void handleUse(MachineBasicBlock& mbb,
|
||||||
|
MachineBasicBlock::iterator mii,
|
||||||
|
unsigned virtReg,
|
||||||
|
unsigned physReg) {
|
||||||
|
// check if we are replacing a previous mapping
|
||||||
|
if (p2vMap_[physReg] != virtReg) {
|
||||||
|
vacatePhysReg(mbb, mii, physReg);
|
||||||
|
p2vMap_[physReg] = virtReg;
|
||||||
|
// load if necessary
|
||||||
|
if (VRM->hasStackSlot(virtReg)) {
|
||||||
|
MRI->loadRegFromStackSlot(mbb, mii, physReg,
|
||||||
|
VRM->getStackSlot(virtReg));
|
||||||
|
++NumLoads;
|
||||||
|
DEBUG(std::cerr << "added: ";
|
||||||
|
prior(mii)->print(std::cerr, TM));
|
||||||
|
lastDef_[virtReg] = mii;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void handleDef(MachineBasicBlock& mbb,
|
||||||
|
MachineBasicBlock::iterator mii,
|
||||||
|
unsigned virtReg,
|
||||||
|
unsigned physReg) {
|
||||||
|
// check if we are replacing a previous mapping
|
||||||
|
if (p2vMap_[physReg] != virtReg)
|
||||||
|
vacatePhysReg(mbb, mii, physReg);
|
||||||
|
|
||||||
|
p2vMap_[physReg] = virtReg;
|
||||||
|
dirty_[physReg] = true;
|
||||||
|
lastDef_[virtReg] = mii;
|
||||||
|
}
|
||||||
|
|
||||||
|
void eliminateVirtRegsInMbb(MachineBasicBlock& mbb);
|
||||||
|
};
|
||||||
|
}
|
||||||
|
|
||||||
|
bool LocalSpiller::runOnMachineFunction(MachineFunction &mf,
|
||||||
|
const VirtRegMap &vrm) {
|
||||||
|
MF = &mf;
|
||||||
|
TM = &MF->getTarget();
|
||||||
|
TII = TM->getInstrInfo();
|
||||||
|
MRI = TM->getRegisterInfo();
|
||||||
|
VRM = &vrm;
|
||||||
|
p2vMap_.assign(MRI->getNumRegs(), 0);
|
||||||
|
dirty_.assign(MRI->getNumRegs(), false);
|
||||||
|
|
||||||
|
DEBUG(std::cerr << "********** REWRITE MACHINE CODE **********\n");
|
||||||
|
DEBUG(std::cerr << "********** Function: "
|
||||||
|
<< MF->getFunction()->getName() << '\n');
|
||||||
|
|
||||||
|
for (MachineFunction::iterator mbbi = MF->begin(),
|
||||||
|
mbbe = MF->end(); mbbi != mbbe; ++mbbi) {
|
||||||
|
lastDef_.grow(MF->getSSARegMap()->getLastVirtReg());
|
||||||
|
DEBUG(std::cerr << mbbi->getBasicBlock()->getName() << ":\n");
|
||||||
|
eliminateVirtRegsInMbb(*mbbi);
|
||||||
|
// clear map, dirty flag and last ref
|
||||||
|
p2vMap_.assign(p2vMap_.size(), 0);
|
||||||
|
dirty_.assign(dirty_.size(), false);
|
||||||
|
lastDef_.clear();
|
||||||
|
}
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
void LocalSpiller::vacateJustPhysReg(MachineBasicBlock& mbb,
|
||||||
|
MachineBasicBlock::iterator mii,
|
||||||
|
unsigned physReg) {
|
||||||
|
unsigned virtReg = p2vMap_[physReg];
|
||||||
|
if (dirty_[physReg] && VRM->hasStackSlot(virtReg)) {
|
||||||
|
assert(lastDef_[virtReg] && "virtual register is mapped "
|
||||||
|
"to a register and but was not defined!");
|
||||||
|
MachineBasicBlock::iterator lastDef = lastDef_[virtReg];
|
||||||
|
MachineBasicBlock::iterator nextLastRef = next(lastDef);
|
||||||
|
MRI->storeRegToStackSlot(*lastDef->getParent(),
|
||||||
|
nextLastRef,
|
||||||
|
physReg,
|
||||||
|
VRM->getStackSlot(virtReg));
|
||||||
|
++NumStores;
|
||||||
|
DEBUG(std::cerr << "added: ";
|
||||||
|
prior(nextLastRef)->print(std::cerr, TM);
|
||||||
|
std::cerr << "after: ";
|
||||||
|
lastDef->print(std::cerr, TM));
|
||||||
|
lastDef_[virtReg] = 0;
|
||||||
|
}
|
||||||
|
p2vMap_[physReg] = 0;
|
||||||
|
dirty_[physReg] = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
void LocalSpiller::eliminateVirtRegsInMbb(MachineBasicBlock &MBB) {
|
||||||
|
for (MachineBasicBlock::iterator MI = MBB.begin(), E = MBB.end();
|
||||||
|
MI != E; ++MI) {
|
||||||
|
|
||||||
|
// if we have references to memory operands make sure
|
||||||
|
// we clear all physical registers that may contain
|
||||||
|
// the value of the spilled virtual register
|
||||||
|
VirtRegMap::MI2VirtMap::const_iterator i, e;
|
||||||
|
for (tie(i, e) = VRM->getFoldedVirts(MI); i != e; ++i) {
|
||||||
|
if (VRM->hasPhys(i->second))
|
||||||
|
vacateJustPhysReg(MBB, MI, VRM->getPhys(i->second));
|
||||||
|
}
|
||||||
|
|
||||||
|
// rewrite all used operands
|
||||||
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||||
|
MachineOperand& op = MI->getOperand(i);
|
||||||
|
if (op.isRegister() && op.getReg() && op.isUse() &&
|
||||||
|
MRegisterInfo::isVirtualRegister(op.getReg())) {
|
||||||
|
unsigned virtReg = op.getReg();
|
||||||
|
unsigned physReg = VRM->getPhys(virtReg);
|
||||||
|
handleUse(MBB, MI, virtReg, physReg);
|
||||||
|
MI->SetMachineOperandReg(i, physReg);
|
||||||
|
// mark as dirty if this is def&use
|
||||||
|
if (op.isDef()) {
|
||||||
|
dirty_[physReg] = true;
|
||||||
|
lastDef_[virtReg] = MI;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// spill implicit physical register defs
|
||||||
|
const TargetInstrDescriptor& tid = TII->get(MI->getOpcode());
|
||||||
|
for (const unsigned* id = tid.ImplicitDefs; *id; ++id)
|
||||||
|
vacatePhysReg(MBB, MI, *id);
|
||||||
|
|
||||||
|
// spill explicit physical register defs
|
||||||
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||||
|
MachineOperand& op = MI->getOperand(i);
|
||||||
|
if (op.isRegister() && op.getReg() && !op.isUse() &&
|
||||||
|
MRegisterInfo::isPhysicalRegister(op.getReg()))
|
||||||
|
vacatePhysReg(MBB, MI, op.getReg());
|
||||||
|
}
|
||||||
|
|
||||||
|
// rewrite def operands (def&use was handled with the
|
||||||
|
// uses so don't check for those here)
|
||||||
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||||
|
MachineOperand& op = MI->getOperand(i);
|
||||||
|
if (op.isRegister() && op.getReg() && !op.isUse())
|
||||||
|
if (MRegisterInfo::isPhysicalRegister(op.getReg()))
|
||||||
|
vacatePhysReg(MBB, MI, op.getReg());
|
||||||
|
else {
|
||||||
|
unsigned physReg = VRM->getPhys(op.getReg());
|
||||||
|
handleDef(MBB, MI, op.getReg(), physReg);
|
||||||
|
MI->SetMachineOperandReg(i, physReg);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
DEBUG(std::cerr << '\t'; MI->print(std::cerr, TM));
|
||||||
|
}
|
||||||
|
|
||||||
|
for (unsigned i = 1, e = p2vMap_.size(); i != e; ++i)
|
||||||
|
vacateJustPhysReg(MBB, MBB.getFirstTerminator(), i);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
llvm::Spiller* llvm::createSpiller() {
|
||||||
|
switch (SpillerOpt) {
|
||||||
|
default: assert(0 && "Unreachable!");
|
||||||
|
case local:
|
||||||
|
return new LocalSpiller();
|
||||||
|
case simple:
|
||||||
|
return new SimpleSpiller();
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
@ -7,125 +7,121 @@
|
|||||||
//
|
//
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
//
|
//
|
||||||
// This file implements a virtual register map. This maps virtual
|
// This file implements a virtual register map. This maps virtual registers to
|
||||||
// registers to physical registers and virtual registers to stack
|
// physical registers and virtual registers to stack slots. It is created and
|
||||||
// slots. It is created and updated by a register allocator and then
|
// updated by a register allocator and then used by a machine code rewriter that
|
||||||
// used by a machine code rewriter that adds spill code and rewrites
|
// adds spill code and rewrites virtual into physical register references.
|
||||||
// virtual into physical register references.
|
|
||||||
//
|
//
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
#ifndef LLVM_CODEGEN_VIRTREGMAP_H
|
#ifndef LLVM_CODEGEN_VIRTREGMAP_H
|
||||||
#define LLVM_CODEGEN_VIRTREGMAP_H
|
#define LLVM_CODEGEN_VIRTREGMAP_H
|
||||||
|
|
||||||
#include "llvm/CodeGen/MachineFunction.h"
|
#include "llvm/Target/MRegisterInfo.h"
|
||||||
#include "llvm/CodeGen/SSARegMap.h"
|
|
||||||
#include "llvm/ADT/DenseMap.h"
|
#include "llvm/ADT/DenseMap.h"
|
||||||
#include <climits>
|
|
||||||
#include <map>
|
#include <map>
|
||||||
|
|
||||||
namespace llvm {
|
namespace llvm {
|
||||||
|
class MachineInstr;
|
||||||
|
|
||||||
class MachineInstr;
|
class VirtRegMap {
|
||||||
|
public:
|
||||||
|
typedef DenseMap<unsigned, VirtReg2IndexFunctor> Virt2PhysMap;
|
||||||
|
typedef DenseMap<int, VirtReg2IndexFunctor> Virt2StackSlotMap;
|
||||||
|
typedef std::multimap<MachineInstr*, unsigned> MI2VirtMap;
|
||||||
|
|
||||||
class VirtRegMap {
|
private:
|
||||||
public:
|
MachineFunction* mf_;
|
||||||
typedef DenseMap<unsigned, VirtReg2IndexFunctor> Virt2PhysMap;
|
Virt2PhysMap v2pMap_;
|
||||||
typedef DenseMap<int, VirtReg2IndexFunctor> Virt2StackSlotMap;
|
Virt2StackSlotMap v2ssMap_;
|
||||||
typedef std::multimap<MachineInstr*, unsigned> MI2VirtMap;
|
MI2VirtMap mi2vMap_;
|
||||||
|
|
||||||
|
VirtRegMap(const VirtRegMap&); // DO NOT IMPLEMENT
|
||||||
|
void operator=(const VirtRegMap&); // DO NOT IMPLEMENT
|
||||||
|
|
||||||
private:
|
enum {
|
||||||
MachineFunction* mf_;
|
NO_PHYS_REG = 0,
|
||||||
Virt2PhysMap v2pMap_;
|
NO_STACK_SLOT = ~0 >> 1
|
||||||
Virt2StackSlotMap v2ssMap_;
|
|
||||||
MI2VirtMap mi2vMap_;
|
|
||||||
|
|
||||||
// do not implement
|
|
||||||
VirtRegMap(const VirtRegMap& rhs);
|
|
||||||
const VirtRegMap& operator=(const VirtRegMap& rhs);
|
|
||||||
|
|
||||||
enum {
|
|
||||||
NO_PHYS_REG = 0,
|
|
||||||
NO_STACK_SLOT = INT_MAX
|
|
||||||
};
|
|
||||||
|
|
||||||
public:
|
|
||||||
VirtRegMap(MachineFunction& mf)
|
|
||||||
: mf_(&mf),
|
|
||||||
v2pMap_(NO_PHYS_REG),
|
|
||||||
v2ssMap_(NO_STACK_SLOT) {
|
|
||||||
grow();
|
|
||||||
}
|
|
||||||
|
|
||||||
void grow() {
|
|
||||||
v2pMap_.grow(mf_->getSSARegMap()->getLastVirtReg());
|
|
||||||
v2ssMap_.grow(mf_->getSSARegMap()->getLastVirtReg());
|
|
||||||
}
|
|
||||||
|
|
||||||
bool hasPhys(unsigned virtReg) const {
|
|
||||||
return getPhys(virtReg) != NO_PHYS_REG;
|
|
||||||
}
|
|
||||||
|
|
||||||
unsigned getPhys(unsigned virtReg) const {
|
|
||||||
assert(MRegisterInfo::isVirtualRegister(virtReg));
|
|
||||||
return v2pMap_[virtReg];
|
|
||||||
}
|
|
||||||
|
|
||||||
void assignVirt2Phys(unsigned virtReg, unsigned physReg) {
|
|
||||||
assert(MRegisterInfo::isVirtualRegister(virtReg) &&
|
|
||||||
MRegisterInfo::isPhysicalRegister(physReg));
|
|
||||||
assert(v2pMap_[virtReg] == NO_PHYS_REG &&
|
|
||||||
"attempt to assign physical register to already mapped "
|
|
||||||
"virtual register");
|
|
||||||
v2pMap_[virtReg] = physReg;
|
|
||||||
}
|
|
||||||
|
|
||||||
void clearVirt(unsigned virtReg) {
|
|
||||||
assert(MRegisterInfo::isVirtualRegister(virtReg));
|
|
||||||
assert(v2pMap_[virtReg] != NO_PHYS_REG &&
|
|
||||||
"attempt to clear a not assigned virtual register");
|
|
||||||
v2pMap_[virtReg] = NO_PHYS_REG;
|
|
||||||
}
|
|
||||||
|
|
||||||
void clearAllVirt() {
|
|
||||||
v2pMap_.clear();
|
|
||||||
grow();
|
|
||||||
}
|
|
||||||
|
|
||||||
bool hasStackSlot(unsigned virtReg) const {
|
|
||||||
return getStackSlot(virtReg) != NO_STACK_SLOT;
|
|
||||||
}
|
|
||||||
|
|
||||||
int getStackSlot(unsigned virtReg) const {
|
|
||||||
assert(MRegisterInfo::isVirtualRegister(virtReg));
|
|
||||||
return v2ssMap_[virtReg];
|
|
||||||
}
|
|
||||||
|
|
||||||
int assignVirt2StackSlot(unsigned virtReg);
|
|
||||||
void assignVirt2StackSlot(unsigned virtReg, int frameIndex);
|
|
||||||
|
|
||||||
void virtFolded(unsigned virtReg,
|
|
||||||
MachineInstr* oldMI,
|
|
||||||
MachineInstr* newMI);
|
|
||||||
|
|
||||||
std::pair<MI2VirtMap::const_iterator, MI2VirtMap::const_iterator>
|
|
||||||
getFoldedVirts(MachineInstr* MI) const {
|
|
||||||
return mi2vMap_.equal_range(MI);
|
|
||||||
}
|
|
||||||
|
|
||||||
friend std::ostream& operator<<(std::ostream& os, const VirtRegMap& li);
|
|
||||||
};
|
};
|
||||||
|
|
||||||
std::ostream& operator<<(std::ostream& os, const VirtRegMap& li);
|
public:
|
||||||
|
VirtRegMap(MachineFunction& mf)
|
||||||
|
: mf_(&mf), v2pMap_(NO_PHYS_REG), v2ssMap_(NO_STACK_SLOT) {
|
||||||
|
grow();
|
||||||
|
}
|
||||||
|
|
||||||
struct Spiller {
|
void grow();
|
||||||
virtual ~Spiller();
|
|
||||||
|
|
||||||
virtual bool runOnMachineFunction(MachineFunction& mf, const VirtRegMap& vrm) = 0;
|
bool hasPhys(unsigned virtReg) const {
|
||||||
|
return getPhys(virtReg) != NO_PHYS_REG;
|
||||||
|
}
|
||||||
|
|
||||||
};
|
unsigned getPhys(unsigned virtReg) const {
|
||||||
|
assert(MRegisterInfo::isVirtualRegister(virtReg));
|
||||||
|
return v2pMap_[virtReg];
|
||||||
|
}
|
||||||
|
|
||||||
Spiller* createSpiller();
|
void assignVirt2Phys(unsigned virtReg, unsigned physReg) {
|
||||||
|
assert(MRegisterInfo::isVirtualRegister(virtReg) &&
|
||||||
|
MRegisterInfo::isPhysicalRegister(physReg));
|
||||||
|
assert(v2pMap_[virtReg] == NO_PHYS_REG &&
|
||||||
|
"attempt to assign physical register to already mapped "
|
||||||
|
"virtual register");
|
||||||
|
v2pMap_[virtReg] = physReg;
|
||||||
|
}
|
||||||
|
|
||||||
|
void clearVirt(unsigned virtReg) {
|
||||||
|
assert(MRegisterInfo::isVirtualRegister(virtReg));
|
||||||
|
assert(v2pMap_[virtReg] != NO_PHYS_REG &&
|
||||||
|
"attempt to clear a not assigned virtual register");
|
||||||
|
v2pMap_[virtReg] = NO_PHYS_REG;
|
||||||
|
}
|
||||||
|
|
||||||
|
void clearAllVirt() {
|
||||||
|
v2pMap_.clear();
|
||||||
|
grow();
|
||||||
|
}
|
||||||
|
|
||||||
|
bool hasStackSlot(unsigned virtReg) const {
|
||||||
|
return getStackSlot(virtReg) != NO_STACK_SLOT;
|
||||||
|
}
|
||||||
|
|
||||||
|
int getStackSlot(unsigned virtReg) const {
|
||||||
|
assert(MRegisterInfo::isVirtualRegister(virtReg));
|
||||||
|
return v2ssMap_[virtReg];
|
||||||
|
}
|
||||||
|
|
||||||
|
int assignVirt2StackSlot(unsigned virtReg);
|
||||||
|
void assignVirt2StackSlot(unsigned virtReg, int frameIndex);
|
||||||
|
|
||||||
|
void virtFolded(unsigned virtReg, MachineInstr* oldMI,
|
||||||
|
MachineInstr* newMI);
|
||||||
|
|
||||||
|
std::pair<MI2VirtMap::const_iterator, MI2VirtMap::const_iterator>
|
||||||
|
getFoldedVirts(MachineInstr* MI) const {
|
||||||
|
return mi2vMap_.equal_range(MI);
|
||||||
|
}
|
||||||
|
|
||||||
|
void print(std::ostream &OS) const;
|
||||||
|
void dump() const;
|
||||||
|
};
|
||||||
|
|
||||||
|
inline std::ostream &operator<<(std::ostream &OS, const VirtRegMap &VRM) {
|
||||||
|
VRM.print(OS);
|
||||||
|
return OS;
|
||||||
|
}
|
||||||
|
|
||||||
|
/// Spiller interface: Implementations of this interface assign spilled
|
||||||
|
/// virtual registers to stack slots, rewriting the code.
|
||||||
|
struct Spiller {
|
||||||
|
virtual ~Spiller();
|
||||||
|
virtual bool runOnMachineFunction(MachineFunction &MF,
|
||||||
|
const VirtRegMap &VRM) = 0;
|
||||||
|
};
|
||||||
|
|
||||||
|
/// createSpiller - Create an return a spiller object, as specified on the
|
||||||
|
/// command line.
|
||||||
|
Spiller* createSpiller();
|
||||||
|
|
||||||
} // End llvm namespace
|
} // End llvm namespace
|
||||||
|
|
||||||
|
Loading…
x
Reference in New Issue
Block a user