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	Use getVectorTypeBreakdown in FunctionLoweringInfo::CreateRegForValue
to compute the number and type of registers needed for vector values instead of computing it manually. This fixes PR1529. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37755 91177308-0d34-0410-b5e6-96231b3b80d8
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		| @@ -306,53 +306,20 @@ FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, | |||||||
| unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { | unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { | ||||||
|   MVT::ValueType VT = TLI.getValueType(V->getType()); |   MVT::ValueType VT = TLI.getValueType(V->getType()); | ||||||
|    |    | ||||||
|   // The number of multiples of registers that we need, to, e.g., split up |   unsigned NumRegisters; | ||||||
|   // a <2 x int64> -> 4 x i32 registers. |   MVT::ValueType RegisterVT; | ||||||
|   unsigned NumVectorRegs = 1; |  | ||||||
|    |  | ||||||
|   // If this is a vector type, figure out what type it will decompose into |  | ||||||
|   // and how many of the elements it will use. |  | ||||||
|   if (MVT::isVector(VT)) { |   if (MVT::isVector(VT)) { | ||||||
|     const VectorType *PTy = cast<VectorType>(V->getType()); |     MVT::ValueType ElementVT; | ||||||
|     unsigned NumElts = PTy->getNumElements(); |     NumRegisters = TLI.getVectorTypeBreakdown(VT, ElementVT, RegisterVT); | ||||||
|     MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType()); |   } else { | ||||||
|     MVT::ValueType VecTy = MVT::getVectorType(EltTy, NumElts); |     RegisterVT = TLI.getTypeToTransformTo(VT); | ||||||
|      |     NumRegisters = TLI.getNumRegisters(VT); | ||||||
|     // Divide the input until we get to a supported size.  This will always |  | ||||||
|     // end with a scalar if the target doesn't support vectors. |  | ||||||
|     while (NumElts > 1 && !TLI.isTypeLegal(VecTy)) { |  | ||||||
|       NumElts >>= 1; |  | ||||||
|       NumVectorRegs <<= 1; |  | ||||||
|       VecTy = MVT::getVectorType(EltTy, NumElts); |  | ||||||
|   } |   } | ||||||
|  |  | ||||||
|     // Check that VecTy isn't a 1-element vector. |   unsigned R = MakeReg(RegisterVT); | ||||||
|     if (NumElts == 1 && VecTy == MVT::Other) |   for (unsigned i = 1; i != NumRegisters; ++i) | ||||||
|       VT = EltTy; |     MakeReg(RegisterVT); | ||||||
|     else |  | ||||||
|       VT = VecTy; |  | ||||||
|   } |  | ||||||
|  |  | ||||||
|   // The common case is that we will only create one register for this |  | ||||||
|   // value.  If we have that case, create and return the virtual register. |  | ||||||
|   unsigned NV = TLI.getNumRegisters(VT); |  | ||||||
|   if (NV == 1) { |  | ||||||
|     // If we are promoting this value, pick the next largest supported type. |  | ||||||
|     MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT); |  | ||||||
|     unsigned Reg = MakeReg(PromotedType); |  | ||||||
|     // If this is a vector of supported or promoted types (e.g. 4 x i16), |  | ||||||
|     // create all of the registers. |  | ||||||
|     for (unsigned i = 1; i != NumVectorRegs; ++i) |  | ||||||
|       MakeReg(PromotedType); |  | ||||||
|     return Reg; |  | ||||||
|   } |  | ||||||
|    |  | ||||||
|   // If this value is represented with multiple target registers, make sure |  | ||||||
|   // to create enough consecutive registers of the right (smaller) type. |  | ||||||
|   VT = TLI.getTypeToExpandTo(VT); |  | ||||||
|   unsigned R = MakeReg(VT); |  | ||||||
|   for (unsigned i = 1; i != NV*NumVectorRegs; ++i) |  | ||||||
|     MakeReg(VT); |  | ||||||
|   return R; |   return R; | ||||||
| } | } | ||||||
|  |  | ||||||
|   | |||||||
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