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Teach tblgen to emit MCRegisterClasses.
- This currently introduces more instances of the static DenseSet dtor, but that should be fixable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135735 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -40,10 +40,15 @@ public:
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unsigned RS, unsigned Al, int CC, bool Allocable,
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iterator RB, iterator RE)
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: ID(id), Name(name), RegSize(RS), Alignment(Al), CopyCost(CC),
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Allocatable(Allocable), RegsBegin(RB), RegsEnd(RE) {
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for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
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RegSet.insert(*I);
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}
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Allocatable(Allocable), RegsBegin(RB), RegsEnd(RE) {}
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/// initMCRegisterClass - Initialize initMCRegisterClass. *DO NOT USE*.
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// FIXME: This could go away if RegSet would use a constant bit field.
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void initMCRegisterClass() {
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RegSet.resize(getNumRegs());
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for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
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RegSet.insert(*I);
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}
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/// getID() - Return the register class ID number.
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///
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@ -128,10 +133,14 @@ struct MCRegisterDesc {
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/// virtual methods.
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///
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class MCRegisterInfo {
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public:
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typedef const MCRegisterClass *regclass_iterator;
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private:
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const MCRegisterDesc *Desc; // Pointer to the descriptor array
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unsigned NumRegs; // Number of entries in the array
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unsigned RAReg; // Return address register
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const MCRegisterClass *Classes; // Pointer to the regclass array
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unsigned NumClasses; // Number of entries in the array
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DenseMap<unsigned, int> L2DwarfRegs; // LLVM to Dwarf regs mapping
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DenseMap<unsigned, int> EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
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DenseMap<unsigned, unsigned> Dwarf2LRegs; // Dwarf to LLVM regs mapping
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@ -141,10 +150,16 @@ private:
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public:
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/// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
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/// auto-generated routines. *DO NOT USE*.
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void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA) {
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void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
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MCRegisterClass *C, unsigned NC) {
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Desc = D;
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NumRegs = NR;
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RAReg = RA;
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Classes = C;
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NumClasses = NC;
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// FIXME: This should go away.
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for (unsigned i = 0; i != NC; ++i)
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C[i].initMCRegisterClass();
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}
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/// mapLLVMRegToDwarfReg - Used to initialize LLVM register to Dwarf
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@ -273,6 +288,20 @@ public:
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if (I == L2SEHRegs.end()) return (int)RegNum;
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return I->second;
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}
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regclass_iterator regclass_begin() const { return Classes; }
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regclass_iterator regclass_end() const { return Classes+NumClasses; }
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unsigned getNumRegClasses() const {
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return (unsigned)(regclass_end()-regclass_begin());
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}
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/// getRegClass - Returns the register class associated with the enumeration
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/// value. See class MCOperandInfo.
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const MCRegisterClass getRegClass(unsigned i) const {
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assert(i < getNumRegClasses() && "Register Class ID out of range");
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return Classes[i];
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}
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};
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} // End llvm namespace
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@ -52,7 +52,9 @@ public:
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iterator RB, iterator RE)
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: MCRegisterClass(id, name, RS, Al, CC, Allocable, RB, RE),
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VTs(vts), SubClasses(subcs), SuperClasses(supcs), SubRegClasses(subregcs),
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SuperRegClasses(superregcs) {}
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SuperRegClasses(superregcs) {
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initMCRegisterClass();
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}
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virtual ~TargetRegisterClass() {} // Allow subclasses
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@ -297,12 +297,62 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
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}
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OS << "};\n\n"; // End of register descriptors...
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// FIXME: This code is duplicated in the TargetRegisterClass emitter.
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const std::vector<CodeGenRegisterClass> &RegisterClasses =
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Target.getRegisterClasses();
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// Loop over all of the register classes... emitting each one.
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OS << "namespace { // Register classes...\n";
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// Emit the register enum value arrays for each RegisterClass
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
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const CodeGenRegisterClass &RC = RegisterClasses[rc];
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ArrayRef<Record*> Order = RC.getOrder();
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// Give the register class a legal C name if it's anonymous.
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std::string Name = RC.getName();
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// Emit the register list now.
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OS << " // " << Name << " Register Class...\n"
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<< " static const unsigned " << Name
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<< "[] = {\n ";
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for (unsigned i = 0, e = Order.size(); i != e; ++i) {
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Record *Reg = Order[i];
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OS << getQualifiedName(Reg) << ", ";
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}
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OS << "\n };\n\n";
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}
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OS << "}\n\n";
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OS << "MCRegisterClass " << TargetName << "MCRegisterClasses[] = {\n";
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
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const CodeGenRegisterClass &RC = RegisterClasses[rc];
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ArrayRef<Record*> Order = RC.getOrder();
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std::string Name = RC.getName();
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OS << " MCRegisterClass("
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<< rc << ", "
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<< '\"' << RC.getName() << "\", "
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<< RC.SpillSize/8 << ", "
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<< RC.SpillAlignment/8 << ", "
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<< RC.CopyCost << ", "
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<< RC.Allocatable << ", "
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<< RC.getName() << ", " << RC.getName() << " + "
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<< RC.getOrder().size()
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<< "),\n";
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}
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OS << "};\n\n";
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// MCRegisterInfo initialization routine.
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OS << "static inline void Init" << TargetName
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<< "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
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<< "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
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OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
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<< Regs.size()+1 << ", RA);\n\n";
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<< Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
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<< RegisterClasses.size() << ");\n\n";
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EmitRegMapping(OS, Regs, false);
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@ -773,6 +823,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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// Emit the constructor of the class...
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OS << "extern MCRegisterDesc " << TargetName << "RegDesc[];\n";
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OS << "extern MCRegisterClass " << TargetName << "MCRegisterClasses[];\n";
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OS << ClassName << "::" << ClassName
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<< "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
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@ -780,7 +831,8 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
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<< " " << TargetName << "SubRegIndexTable) {\n"
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<< " InitMCRegisterInfo(" << TargetName << "RegDesc, "
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<< Regs.size()+1 << ", RA);\n\n";
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<< Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
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<< RegisterClasses.size() << ");\n\n";
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EmitRegMapping(OS, Regs, true);
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@ -50,6 +50,7 @@ public:
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private:
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void EmitRegMapping(raw_ostream &o,
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const std::vector<CodeGenRegister*> &Regs, bool isCtor);
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void EmitRegClasses(raw_ostream &OS, CodeGenTarget &Target);
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};
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} // End llvm namespace
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