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Add readcyclecounter lowering on PPC64.

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On PPC64, this can be done with a simple TableGen pattern.
To enable this, I've added the (otherwise missing) readcyclecounter
SDNode definition to TargetSelectionDAG.td.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161302 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2012-08-04 14:10:46 +00:00
parent ad62e92279
commit 8cc3474f72
4 changed files with 26 additions and 1 deletions
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3
include/llvm/Target/TargetSelectionDAG.td
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@ -411,6 +411,9 @@ def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch,
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
SDNPMemOperand]>; SDNPMemOperand]>;
def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf,
[SDNPHasChain, SDNPSideEffect]>;
def membarrier : SDNode<"ISD::MEMBARRIER" , SDTMemBarrier, def membarrier : SDNode<"ISD::MEMBARRIER" , SDTMemBarrier,
[SDNPHasChain, SDNPSideEffect]>; [SDNPHasChain, SDNPSideEffect]>;

4
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -394,8 +394,10 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
} }
if (Subtarget->has64BitSupport()) if (Subtarget->has64BitSupport()) {
setOperationAction(ISD::PREFETCH, MVT::Other, Legal); setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
}
setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);

5
lib/Target/PowerPC/PPCInstr64Bit.td
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@ -265,6 +265,11 @@ def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS),
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
} }
let Pattern = [(set G8RC:$rT, readcyclecounter)] in
def MFTB8 : XFXForm_1_ext<31, 371, 268, (outs G8RC:$rT), (ins),
"mftb $rT", SprMFTB>,
PPC970_DGroup_First, PPC970_Unit_FXU;
let Defs = [X1], Uses = [X1] in let Defs = [X1], Uses = [X1] in
def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"", def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"",
[(set G8RC:$result, [(set G8RC:$result,

15
test/CodeGen/PowerPC/ppc64-cyclecounter.ll Normal file
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@ -0,0 +1,15 @@
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
; RUN: llc < %s | FileCheck %s
define i64 @test1() nounwind {
entry:
%r = call i64 @llvm.readcyclecounter()
ret i64 %r
}
; CHECK: @test1
; CHECK: mftb
declare i64 @llvm.readcyclecounter()