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Fix an assertion failure when optimising a shufflevector incorrectly into concat_vectors, and a followup bug with SelectionDAG::getNode() creating nodes with invalid types.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163511 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
James Molloy
2012-09-10 14:01:21 +00:00
parent ff1b63172d
commit 8cd08bf4ac
3 changed files with 22 additions and 10 deletions
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6
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@@ -8095,6 +8095,12 @@ SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits()) if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits())
return SDValue(); return SDValue();
// If the input vector type has a different base type to the output
// vector type, bail out.
if (VecIn1.getValueType().getVectorElementType() !=
VT.getVectorElementType())
return SDValue();
// Widen the input vector by adding undef values. // Widen the input vector by adding undef values.
VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
VecIn1, DAG.getUNDEF(VecIn1.getValueType())); VecIn1, DAG.getUNDEF(VecIn1.getValueType()));

16
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@@ -2934,17 +2934,13 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
// expanding large vector constants. // expanding large vector constants.
if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) { if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) {
SDValue Elt = N1.getOperand(N2C->getZExtValue()); SDValue Elt = N1.getOperand(N2C->getZExtValue());
EVT VEltTy = N1.getValueType().getVectorElementType();
if (Elt.getValueType() != VEltTy) { if (VT != Elt.getValueType())
// If the vector element type is not legal, the BUILD_VECTOR operands // If the vector element type is not legal, the BUILD_VECTOR operands
// are promoted and implicitly truncated. Make that explicit here. // are promoted and implicitly truncated, and the result implicitly
Elt = getNode(ISD::TRUNCATE, DL, VEltTy, Elt); // extended. Make that explicit here.
} Elt = getAnyExtOrTrunc(Elt, DL, VT);
if (VT != VEltTy) {
// If the vector element type is not legal, the EXTRACT_VECTOR_ELT
// result is implicitly extended.
Elt = getNode(ISD::ANY_EXTEND, DL, VT, Elt);
}
return Elt; return Elt;
} }

10
test/CodeGen/ARM/crash-shufflevector.ll Normal file
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@@ -0,0 +1,10 @@
; RUN: llc < %s -mtriple=armv7
declare void @g(<16 x i8>)
define void @f(<4 x i8> %param1, <4 x i8> %param2) {
%y1 = shufflevector <4 x i8> %param1, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%y2 = shufflevector <4 x i8> %param2, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%z = shufflevector <16 x i8> %y1, <16 x i8> %y2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19>
call void @g(<16 x i8> %z)
ret void
}