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Minor cleanups to reduce some spurious differences between different
scheduler implementations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41191 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -45,7 +45,6 @@ namespace {
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/// ScheduleDAGRRList - The actual register reduction list scheduler
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/// ScheduleDAGRRList - The actual register reduction list scheduler
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/// implementation. This supports both top-down and bottom-up scheduling.
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/// implementation. This supports both top-down and bottom-up scheduling.
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///
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///
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class VISIBILITY_HIDDEN ScheduleDAGRRList : public ScheduleDAG {
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class VISIBILITY_HIDDEN ScheduleDAGRRList : public ScheduleDAG {
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private:
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private:
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/// isBottomUp - This is true if the scheduling problem is bottom-up, false if
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/// isBottomUp - This is true if the scheduling problem is bottom-up, false if
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@ -95,7 +94,7 @@ void ScheduleDAGRRList::Schedule() {
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CalculateHeights();
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CalculateHeights();
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AvailableQueue->initNodes(SUnitMap, SUnits);
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AvailableQueue->initNodes(SUnitMap, SUnits);
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// Execute the actual scheduling loop Top-Down or Bottom-Up as appropriate.
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// Execute the actual scheduling loop Top-Down or Bottom-Up as appropriate.
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if (isBottomUp)
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if (isBottomUp)
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ListScheduleBottomUp();
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ListScheduleBottomUp();
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@ -103,7 +102,7 @@ void ScheduleDAGRRList::Schedule() {
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ListScheduleTopDown();
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ListScheduleTopDown();
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AvailableQueue->releaseState();
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AvailableQueue->releaseState();
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CommuteNodesToReducePressure();
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CommuteNodesToReducePressure();
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DOUT << "*** Final schedule ***\n";
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DOUT << "*** Final schedule ***\n";
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@ -169,7 +168,7 @@ void ScheduleDAGRRList::CommuteNodesToReducePressure() {
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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/// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
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/// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
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/// the Available queue is the count reaches zero. Also update its cycle bound.
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/// the AvailableQueue if the count reaches zero. Also update its cycle bound.
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void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain,
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void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain,
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unsigned CurCycle) {
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unsigned CurCycle) {
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// FIXME: the distance between two nodes is not always == the predecessor's
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// FIXME: the distance between two nodes is not always == the predecessor's
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@ -233,7 +232,7 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
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AvailableQueue->push(SUnitMap[DAG.getRoot().Val]);
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AvailableQueue->push(SUnitMap[DAG.getRoot().Val]);
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// While Available queue is not empty, grab the node with the highest
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// While Available queue is not empty, grab the node with the highest
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// priority. If it is not ready put it back. Schedule the node.
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// priority. If it is not ready put it back. Schedule the node.
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std::vector<SUnit*> NotReady;
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std::vector<SUnit*> NotReady;
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while (!AvailableQueue->empty()) {
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while (!AvailableQueue->empty()) {
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SUnit *CurNode = AvailableQueue->pop();
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SUnit *CurNode = AvailableQueue->pop();
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@ -282,7 +281,7 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
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/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
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/// the PendingQueue if the count reaches zero.
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/// the AvailableQueue if the count reaches zero. Also update its cycle bound.
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void ScheduleDAGRRList::ReleaseSucc(SUnit *SuccSU, bool isChain,
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void ScheduleDAGRRList::ReleaseSucc(SUnit *SuccSU, bool isChain,
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unsigned CurCycle) {
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unsigned CurCycle) {
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// FIXME: the distance between two nodes is not always == the predecessor's
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// FIXME: the distance between two nodes is not always == the predecessor's
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@ -330,6 +329,8 @@ void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
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SU->isScheduled = true;
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SU->isScheduled = true;
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}
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}
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/// ListScheduleTopDown - The main loop of list scheduling for top-down
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/// schedulers.
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void ScheduleDAGRRList::ListScheduleTopDown() {
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void ScheduleDAGRRList::ListScheduleTopDown() {
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unsigned CurCycle = 0;
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unsigned CurCycle = 0;
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SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
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SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
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@ -348,7 +349,7 @@ void ScheduleDAGRRList::ListScheduleTopDown() {
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CurCycle++;
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CurCycle++;
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// While Available queue is not empty, grab the node with the highest
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// While Available queue is not empty, grab the node with the highest
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// priority. If it is not ready put it back. Schedule the node.
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// priority. If it is not ready put it back. Schedule the node.
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std::vector<SUnit*> NotReady;
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std::vector<SUnit*> NotReady;
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while (!AvailableQueue->empty()) {
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while (!AvailableQueue->empty()) {
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SUnit *CurNode = AvailableQueue->pop();
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SUnit *CurNode = AvailableQueue->pop();
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@ -474,7 +475,7 @@ namespace {
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const TargetInstrInfo *TII;
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const TargetInstrInfo *TII;
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public:
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public:
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BURegReductionPriorityQueue(const TargetInstrInfo *tii)
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explicit BURegReductionPriorityQueue(const TargetInstrInfo *tii)
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: TII(tii) {}
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: TII(tii) {}
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void initNodes(DenseMap<SDNode*, SUnit*> &sumap,
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void initNodes(DenseMap<SDNode*, SUnit*> &sumap,
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@ -539,7 +540,8 @@ namespace {
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template<class SF>
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template<class SF>
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class TDRegReductionPriorityQueue : public RegReductionPriorityQueue<SF> {
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class VISIBILITY_HIDDEN TDRegReductionPriorityQueue
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: public RegReductionPriorityQueue<SF> {
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// SUnitMap SDNode to SUnit mapping (n -> 1).
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// SUnitMap SDNode to SUnit mapping (n -> 1).
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DenseMap<SDNode*, SUnit*> *SUnitMap;
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DenseMap<SDNode*, SUnit*> *SUnitMap;
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