From 8d5acb7007decaf0c30bf4a3d4c55e5cc2cce0a7 Mon Sep 17 00:00:00 2001
From: Bill Wendling <isanbard@gmail.com>
Date: Sat, 6 Nov 2010 19:56:04 +0000
Subject: [PATCH] Add a RegList (register list) object to ARMOperand. It will
 be used soon to hold (surprise!) a list of registers. Register lists are
 consecutive, so we only need to record the start register plus the number of
 registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118351 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 39 ++++++++++++++++++++++-
 1 file changed, 38 insertions(+), 1 deletion(-)

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 8b16d63ead9..86a1bb679a6 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -42,7 +42,6 @@ class ARMAsmParser : public TargetAsmParser {
   MCAsmParser &Parser;
   TargetMachine &TM;
 
-private:
   MCAsmParser &getParser() const { return Parser; }
 
   MCAsmLexer &getLexer() const { return Parser.getLexer(); }
@@ -118,6 +117,7 @@ public:
     Immediate,
     Memory,
     Register,
+    RegisterList,
     Token
   } Kind;
 
@@ -138,6 +138,11 @@ public:
       bool Writeback;
     } Reg;
 
+     struct {
+      unsigned RegStart;
+      unsigned Number;
+    } RegList;
+
     struct {
       const MCExpr *Val;
     } Imm;
@@ -174,6 +179,9 @@ public:
     case Register:
       Reg = o.Reg;
       break;
+    case RegisterList:
+      RegList = o.RegList;
+      break;
     case Immediate:
       Imm = o.Imm;
       break;
@@ -203,6 +211,11 @@ public:
     return Reg.RegNum;
   }
 
+  std::pair<unsigned, unsigned> getRegList() const {
+    assert(Kind == RegisterList && "Invalid access!");
+    return std::make_pair(RegList.RegStart, RegList.Number);
+  }
+
   const MCExpr *getImm() const {
     assert(Kind == Immediate && "Invalid access!");
     return Imm.Val;
@@ -211,6 +224,7 @@ public:
   bool isCondCode() const { return Kind == CondCode; }
   bool isImm() const { return Kind == Immediate; }
   bool isReg() const { return Kind == Register; }
+  bool isRegList() const { return Kind == RegisterList; }
   bool isToken() const { return Kind == Token; }
   bool isMemory() const { return Kind == Memory; }
 
@@ -312,6 +326,16 @@ public:
     return Op;
   }
 
+  static ARMOperand *CreateRegList(unsigned RegStart, unsigned Number,
+                                   SMLoc S, SMLoc E) {
+    ARMOperand *Op = new ARMOperand(RegisterList);
+    Op->RegList.RegStart = RegStart;
+    Op->RegList.Number = Number;
+    Op->StartLoc = S;
+    Op->EndLoc = E;
+    return Op;
+  }
+
   static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
     ARMOperand *Op = new ARMOperand(Immediate);
     Op->Imm.Val = Val;
@@ -364,6 +388,19 @@ void ARMOperand::dump(raw_ostream &OS) const {
   case Register:
     OS << "<register " << getReg() << ">";
     break;
+  case RegisterList: {
+    OS << "<register_list ";
+    std::pair<unsigned, unsigned> List = getRegList();
+    unsigned RegEnd = List.first + List.second;
+
+    for (unsigned Idx = List.first; Idx < RegEnd; ) {
+      OS << Idx;
+      if (++Idx < RegEnd) OS << ", ";
+    }
+
+    OS << ">";
+    break;
+  }
   case Token:
     OS << "'" << getToken() << "'";
     break;