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[ARM, inline-asm] Fix ARMTargetLowering::getRegForInlineAsmConstraint to return

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register class tGPRRegClass if the target is thumb1.

This commit fixes a crash that occurs during register allocation which was
triggered when a virtual register defined by an inline-asm instruction had to
be spilled.
 
rdar://problem/18740489


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221178 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2014-11-03 20:37:04 +00:00
parent cce85e19f9
commit 8d7cc6b0ff
2 changed files with 14 additions and 1 deletions
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2
lib/Target/ARM/ARMISelLowering.cpp
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@ -10557,6 +10557,8 @@ ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
return RCPair(0U, &ARM::hGPRRegClass);
break;
case 'r':
if (Subtarget->isThumb1Only())
return RCPair(0U, &ARM::tGPRRegClass);
return RCPair(0U, &ARM::GPRRegClass);
case 'w':
if (VT == MVT::Other)

13
test/CodeGen/Thumb/inlineasm-thumb.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s
; RUN: llc -mtriple=thumb-eabi -no-integrated-as %s -o - | FileCheck %s
define i32 @t1(i32 %x, i32 %y) nounwind {
entry:
@ -6,3 +6,14 @@ entry:
%0 = tail call i32 asm "mov $0, $1", "=l,h"(i32 %y) nounwind
ret i32 %0
}
; CHECK-LABEL: constraint_r:
; CHECK: foo2 r{{[0-7]+}}, r{{[0-7]+}}
define i32 @constraint_r() {
entry:
%0 = tail call i32 asm sideeffect "movs $0, #1", "=r"()
tail call void asm sideeffect "foo1", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7}"()
%1 = tail call i32 asm sideeffect "foo2 $0, $1", "=r,r"(i32 %0)
ret i32 %1
}