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Woo, it kinda works. We now generate this atrociously bad, but correct,

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code for long long foo(long long a, long long b) { return a + b; }

_foo:
        or r2, r3, r3
        or r3, r4, r4
        or r4, r5, r5
        or r5, r6, r6
        rldicr r2, r2, 32, 31
        rldicl r3, r3, 0, 32
        rldicr r4, r4, 32, 31
        rldicl r5, r5, 0, 32
        or r2, r3, r2
        or r3, r5, r4
        add r4, r3, r2
        rldicl r2, r4, 32, 32
        or r4, r4, r4
        or r3, r2, r2
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23809 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2005-10-19 01:12:32 +00:00
parent 07c375d6f6
commit 8d94832394
2 changed files with 54 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

59
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -1215,31 +1215,30 @@ SDOperand PPCDAGToDAGISel::Select(SDOperand Op) {
assert(N->getValueType(0) == MVT::i32 &&
N->getOperand(0).getValueType() == MVT::i64 &&
"TRUNCATE only supported for i64 -> i32");
// FIXME: this code breaks ScheduleDAG since Op0 is an i64 and OR4
// takes i32s.
SDOperand Op0 = Select(N->getOperand(0));
CurDAG->SelectNodeTo(N, PPC::OR4, MVT::i32, Op0, Op0);
CurDAG->SelectNodeTo(N, PPC::OR8To4, MVT::i32, Op0, Op0);
break;
}
case ISD::ANY_EXTEND:
switch(N->getValueType(0)) {
default: assert(0 && "Unhandled type in ANY_EXTEND");
case MVT::i64: {
// FIXME: this code breaks ScheduleDAG since Op0 is an i32 and OR8
// takes i64s.
SDOperand Op0 = Select(N->getOperand(0));
CurDAG->SelectNodeTo(N, PPC::OR8, MVT::i64, Op0, Op0);
CurDAG->SelectNodeTo(N, PPC::OR4To8, MVT::i64, Op0, Op0);
break;
}
}
return SDOperand(N, 0);
case ISD::ZERO_EXTEND:
case ISD::ZERO_EXTEND: {
assert(N->getValueType(0) == MVT::i64 &&
N->getOperand(0).getValueType() == MVT::i32 &&
"ZERO_EXTEND only supported for i32 -> i64");
CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Select(N->getOperand(0)),
SDOperand Op0 = Select(N->getOperand(0));
Op0 = CurDAG->getTargetNode(PPC::OR4To8, MVT::i64, Op0, Op0);
CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Op0, getI32Imm(0),
getI32Imm(32));
return SDOperand(N, 0);
}
case ISD::SHL: {
unsigned Imm, SH, MB, ME;
if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
@ -1247,12 +1246,21 @@ SDOperand PPCDAGToDAGISel::Select(SDOperand Op) {
CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
Select(N->getOperand(0).getOperand(0)),
getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
else if (isIntImmediate(N->getOperand(1), Imm))
CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Select(N->getOperand(0)),
getI32Imm(Imm), getI32Imm(0), getI32Imm(31-Imm));
else
CurDAG->SelectNodeTo(N, PPC::SLW, MVT::i32, Select(N->getOperand(0)),
Select(N->getOperand(1)));
else if (isIntImmediate(N->getOperand(1), Imm)) {
if (N->getValueType(0) == MVT::i64)
CurDAG->SelectNodeTo(N, PPC::RLDICR, MVT::i64, Select(N->getOperand(0)),
getI32Imm(Imm), getI32Imm(63-Imm));
else
CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Select(N->getOperand(0)),
getI32Imm(Imm), getI32Imm(0), getI32Imm(31-Imm));
} else {
if (N->getValueType(0) == MVT::i64)
CurDAG->SelectNodeTo(N, PPC::SLD, MVT::i64, Select(N->getOperand(0)),
Select(N->getOperand(1)));
else
CurDAG->SelectNodeTo(N, PPC::SLW, MVT::i32, Select(N->getOperand(0)),
Select(N->getOperand(1)));
}
return SDOperand(N, 0);
}
case ISD::SRL: {
@ -1262,13 +1270,22 @@ SDOperand PPCDAGToDAGISel::Select(SDOperand Op) {
CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
Select(N->getOperand(0).getOperand(0)),
getI32Imm(SH & 0x1F), getI32Imm(MB), getI32Imm(ME));
else if (isIntImmediate(N->getOperand(1), Imm))
CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Select(N->getOperand(0)),
getI32Imm((32-Imm) & 0x1F), getI32Imm(Imm),
getI32Imm(31));
else
CurDAG->SelectNodeTo(N, PPC::SRW, MVT::i32, Select(N->getOperand(0)),
Select(N->getOperand(1)));
else if (isIntImmediate(N->getOperand(1), Imm)) {
if (N->getValueType(0) == MVT::i64)
CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Select(N->getOperand(0)),
getI32Imm(64-Imm), getI32Imm(Imm));
else
CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Select(N->getOperand(0)),
getI32Imm((32-Imm) & 0x1F), getI32Imm(Imm),
getI32Imm(31));
} else {
if (N->getValueType(0) == MVT::i64)
CurDAG->SelectNodeTo(N, PPC::SRD, MVT::i64, Select(N->getOperand(0)),
Select(N->getOperand(1)));
else
CurDAG->SelectNodeTo(N, PPC::SRW, MVT::i32, Select(N->getOperand(0)),
Select(N->getOperand(1)));
}
return SDOperand(N, 0);
}
case ISD::FNEG: {

18
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -18,6 +18,15 @@ include "PPCInstrFormats.td"
//===----------------------------------------------------------------------===//
// PowerPC specific transformation functions and pattern fragments.
//
def GET_ZERO : SDNodeXForm<imm, [{
// Transformation function: get the low 16 bits.
return getI32Imm(0);
}]>;
def GET_32 : SDNodeXForm<imm, [{
// Transformation function: get the low 16 bits.
return getI32Imm(32);
}]>;
def LO16 : SDNodeXForm<imm, [{
// Transformation function: get the low 16 bits.
return getI32Imm((unsigned short)N->getValue());
@ -332,6 +341,12 @@ def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
"or $rA, $rS, $rB",
[(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
"or $rA, $rS, $rB",
[]>;
def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
"or $rA, $rS, $rB",
[]>;
def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"nor $rA, $rS, $rB",
[(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
@ -701,8 +716,7 @@ def : Pat<(or GPRC:$in, imm:$imm),
// XOR an arbitrary immediate.
def : Pat<(xor GPRC:$in, imm:$imm),
(XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
// Same as above, but using a temporary. FIXME: implement temporaries :)
/*
def : Pattern<(xor GPRC:$in, imm:$imm),