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Add instruction encodings / disassembly support for u6 / lu6 instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173086 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne
2013-01-21 20:44:17 +00:00
parent 9b709f8b3f
commit 8da5434346
3 changed files with 93 additions and 60 deletions
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50
test/MC/Disassembler/XCore/xcore.txt
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@@ -392,3 +392,53 @@
# CHECK: stw r0, sp[8761]
0x88 0xf0 0x39 0x54
# u6 / lu6 instructions
# CHECK: bu -20
0x14 0x77
# CHECK: bu -1000
0x0f 0xf0 0x28 0x77
# CHECK: bu 24
0x18 0x73
# CHECK: bu 2231
0x22 0xf0 0x37 0x73
# CHECK: extsp 9
0x89 0x77
# CHECK: extsp 5721
0x59 0xf0 0x99 0x77
# CHECK: clrsr 60
0x3c 0x7b
# CHECK: clrsr 64391
0xee 0xf3 0x07 0x7b
# CHECK: entsp 1
0x41 0x77
# CHECK: entsp 70
0x01 0xf0 0x46 0x77
# CHECK: ldaw r11, cp[5]
0x45 0x7f
# CHECK: ldaw r11, cp[33000]
0x03 0xf2 0x68 0x7f
# CHECK: retsp 40
0xe8 0x77
# CHECK: retsp 52010
0x2c 0xf3 0xea 0x77
# CHECK: setsr 42
0x6a 0x7b
# CHECK: setsr 21863
0x55 0xf1 0x67 0x7b