From 8dbda0b51b7a7a7b4fb16a34b421a658cb86f9f3 Mon Sep 17 00:00:00 2001 From: Johnny Chen Date: Thu, 7 Apr 2011 19:02:08 +0000 Subject: [PATCH] Add sanity checking for invalid register encodings for saturating instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129096 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 5 +++++ test/MC/Disassembler/ARM/invalid-SSAT-arm.txt | 11 +++++++++++ 2 files changed, 16 insertions(+) create mode 100644 test/MC/Disassembler/ARM/invalid-SSAT-arm.txt diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index f4fa3de2684..4933a60ee58 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -1546,6 +1546,11 @@ static bool DisassembleArithMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, static bool DisassembleSatFrm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { + // A8.6.183 SSAT + // if d == 15 || n == 15 then UNPREDICTABLE; + if (decodeRd(insn) == 15 || decodeRm(insn) == 15) + return false; + const TargetInstrDesc &TID = ARMInsts[Opcode]; NumOpsAdded = TID.getNumOperands() - 2; // ignore predicate operands diff --git a/test/MC/Disassembler/ARM/invalid-SSAT-arm.txt b/test/MC/Disassembler/ARM/invalid-SSAT-arm.txt new file mode 100644 index 00000000000..9cc8351b781 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-SSAT-arm.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=322 Name=SSAT Format=ARM_FORMAT_SATFRM(13) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 1| 1: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.183 SSAT +# if d == 15 || n == 15 then UNPREDICTABLE; +0x1a 0xf4 0xa0 0xe6