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Add sanity checking for invalid register encodings for saturating instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129096 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen
2011-04-07 19:02:08 +00:00
parent e815dab69f
commit 8dbda0b51b
2 changed files with 16 additions and 0 deletions
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5
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
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@ -1546,6 +1546,11 @@ static bool DisassembleArithMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
static bool DisassembleSatFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
// A8.6.183 SSAT
// if d == 15 || n == 15 then UNPREDICTABLE;
if (decodeRd(insn) == 15 || decodeRm(insn) == 15)
return false;
const TargetInstrDesc &TID = ARMInsts[Opcode];
NumOpsAdded = TID.getNumOperands() - 2; // ignore predicate operands