mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-01 00:33:09 +00:00
Split several PPC instruction classes.
Slight reorganisation of PPC instruction classes for scheduling. No functionality change for existing subtargets. - Clearly separate load/store-with-update instructions from regular loads and stores. - Split IntRotateD -> IntRotateD and IntRotateDI - Split out fsub and fadd from FPGeneral -> FPAddSub - Update existing itineraries Patch by Tobias von Koch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162729 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel
parent
1d522388bf
commit
8dc440a46a
@ -461,7 +461,7 @@ def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS),
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let Defs = [CARRY] in {
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def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH),
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"sradi $rA, $rS, $SH", IntRotateD,
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"sradi $rA, $rS, $SH", IntRotateDI,
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[(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64;
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}
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def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS),
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@ -484,7 +484,7 @@ def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
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let isCommutable = 1 in {
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def RLDIMI : MDForm_1<30, 3,
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(outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
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"rldimi $rA, $rS, $SH, $MB", IntRotateD,
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"rldimi $rA, $rS, $SH, $MB", IntRotateDI,
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[]>, isPPC64, RegConstraint<"$rSi = $rA">,
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NoEncode<"$rSi">;
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}
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@ -496,11 +496,11 @@ def RLDCL : MDForm_1<30, 0,
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[]>, isPPC64;
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def RLDICL : MDForm_1<30, 0,
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(outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MB),
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"rldicl $rA, $rS, $SH, $MB", IntRotateD,
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"rldicl $rA, $rS, $SH, $MB", IntRotateDI,
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[]>, isPPC64;
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def RLDICR : MDForm_1<30, 1,
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(outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$ME),
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"rldicr $rA, $rS, $SH, $ME", IntRotateD,
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"rldicr $rA, $rS, $SH, $ME", IntRotateDI,
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[]>, isPPC64;
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def RLWINM8 : MForm_2<21,
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@ -543,19 +543,19 @@ def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src),
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let mayLoad = 1 in
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def LHAU8 : DForm_1a<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp,
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ptr_rc:$rA),
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"lhau $rD, $disp($rA)", LdStLoad,
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"lhau $rD, $disp($rA)", LdStLHAU,
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[]>, RegConstraint<"$rA = $ea_result">,
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NoEncode<"$ea_result">;
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// NO LWAU!
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def LHAUX8 : XForm_1<31, 375, (outs G8RC:$rD, ptr_rc:$ea_result),
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(ins memrr:$addr),
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"lhaux $rD, $addr", LdStLoad,
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"lhaux $rD, $addr", LdStLHAU,
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[]>, RegConstraint<"$addr.offreg = $ea_result">,
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NoEncode<"$ea_result">;
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def LWAUX : XForm_1<31, 375, (outs G8RC:$rD, ptr_rc:$ea_result),
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(ins memrr:$addr),
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"lwaux $rD, $addr", LdStLoad,
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"lwaux $rD, $addr", LdStLHAU,
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[]>, RegConstraint<"$addr.offreg = $ea_result">,
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NoEncode<"$ea_result">, isPPC64;
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}
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@ -586,31 +586,31 @@ def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src),
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// Update forms.
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let mayLoad = 1 in {
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def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
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"lbzu $rD, $addr", LdStLoad,
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"lbzu $rD, $addr", LdStLoadUpd,
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[]>, RegConstraint<"$addr.reg = $ea_result">,
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NoEncode<"$ea_result">;
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def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
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"lhzu $rD, $addr", LdStLoad,
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"lhzu $rD, $addr", LdStLoadUpd,
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[]>, RegConstraint<"$addr.reg = $ea_result">,
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NoEncode<"$ea_result">;
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def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
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"lwzu $rD, $addr", LdStLoad,
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"lwzu $rD, $addr", LdStLoadUpd,
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[]>, RegConstraint<"$addr.reg = $ea_result">,
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NoEncode<"$ea_result">;
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def LBZUX8 : XForm_1<31, 119, (outs G8RC:$rD, ptr_rc:$ea_result),
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(ins memrr:$addr),
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"lbzux $rD, $addr", LdStLoad,
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"lbzux $rD, $addr", LdStLoadUpd,
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[]>, RegConstraint<"$addr.offreg = $ea_result">,
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NoEncode<"$ea_result">;
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def LHZUX8 : XForm_1<31, 331, (outs G8RC:$rD, ptr_rc:$ea_result),
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(ins memrr:$addr),
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"lhzux $rD, $addr", LdStLoad,
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"lhzux $rD, $addr", LdStLoadUpd,
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[]>, RegConstraint<"$addr.offreg = $ea_result">,
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NoEncode<"$ea_result">;
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def LWZUX8 : XForm_1<31, 55, (outs G8RC:$rD, ptr_rc:$ea_result),
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(ins memrr:$addr),
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"lwzux $rD, $addr", LdStLoad,
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"lwzux $rD, $addr", LdStLoadUpd,
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[]>, RegConstraint<"$addr.offreg = $ea_result">,
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NoEncode<"$ea_result">;
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}
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@ -652,13 +652,13 @@ def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
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let mayLoad = 1 in
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def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr),
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"ldu $rD, $addr", LdStLD,
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"ldu $rD, $addr", LdStLDU,
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[]>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
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NoEncode<"$ea_result">;
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def LDUX : XForm_1<31, 53, (outs G8RC:$rD, ptr_rc:$ea_result),
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(ins memrr:$addr),
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"ldux $rD, $addr", LdStLoad,
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"ldux $rD, $addr", LdStLDU,
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[]>, RegConstraint<"$addr.offreg = $ea_result">,
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NoEncode<"$ea_result">, isPPC64;
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}
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@ -705,14 +705,14 @@ let PPC970_Unit = 2 in {
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def STBU8 : DForm_1a<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
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symbolLo:$ptroff, ptr_rc:$ptrreg),
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"stbu $rS, $ptroff($ptrreg)", LdStStore,
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"stbu $rS, $ptroff($ptrreg)", LdStStoreUpd,
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[(set ptr_rc:$ea_res,
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(pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg,
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iaddroff:$ptroff))]>,
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RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
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def STHU8 : DForm_1a<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
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symbolLo:$ptroff, ptr_rc:$ptrreg),
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"sthu $rS, $ptroff($ptrreg)", LdStStore,
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"sthu $rS, $ptroff($ptrreg)", LdStStoreUpd,
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[(set ptr_rc:$ea_res,
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(pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg,
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iaddroff:$ptroff))]>,
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@ -720,7 +720,7 @@ def STHU8 : DForm_1a<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
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def STWU8 : DForm_1a<37, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
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symbolLo:$ptroff, ptr_rc:$ptrreg),
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"stwu $rS, $ptroff($ptrreg)", LdStStore,
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"stwu $rS, $ptroff($ptrreg)", LdStStoreUpd,
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[(set ptr_rc:$ea_res,
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(pre_truncsti32 G8RC:$rS, ptr_rc:$ptrreg,
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iaddroff:$ptroff))]>,
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@ -728,7 +728,7 @@ def STWU8 : DForm_1a<37, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
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def STDU : DSForm_1a<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
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s16immX4:$ptroff, ptr_rc:$ptrreg),
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"stdu $rS, $ptroff($ptrreg)", LdStSTD,
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"stdu $rS, $ptroff($ptrreg)", LdStSTDU,
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[(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
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iaddroff:$ptroff))]>,
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RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
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@ -737,7 +737,7 @@ def STDU : DSForm_1a<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
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def STBUX8 : XForm_8<31, 247, (outs ptr_rc:$ea_res),
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(ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
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"stbux $rS, $ptroff, $ptrreg", LdStStore,
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"stbux $rS, $ptroff, $ptrreg", LdStStoreUpd,
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[(set ptr_rc:$ea_res,
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(pre_truncsti8 G8RC:$rS,
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ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
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@ -746,7 +746,7 @@ def STBUX8 : XForm_8<31, 247, (outs ptr_rc:$ea_res),
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def STHUX8 : XForm_8<31, 439, (outs ptr_rc:$ea_res),
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(ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
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"sthux $rS, $ptroff, $ptrreg", LdStStore,
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"sthux $rS, $ptroff, $ptrreg", LdStStoreUpd,
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[(set ptr_rc:$ea_res,
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(pre_truncsti16 G8RC:$rS,
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ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
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@ -755,7 +755,7 @@ def STHUX8 : XForm_8<31, 439, (outs ptr_rc:$ea_res),
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def STWUX8 : XForm_8<31, 183, (outs ptr_rc:$ea_res),
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(ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
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"stwux $rS, $ptroff, $ptrreg", LdStStore,
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"stwux $rS, $ptroff, $ptrreg", LdStStoreUpd,
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[(set ptr_rc:$ea_res,
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(pre_truncsti32 G8RC:$rS,
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ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
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@ -764,7 +764,7 @@ def STWUX8 : XForm_8<31, 183, (outs ptr_rc:$ea_res),
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def STDUX : XForm_8<31, 181, (outs ptr_rc:$ea_res),
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(ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
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"stdux $rS, $ptroff, $ptrreg", LdStStore,
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"stdux $rS, $ptroff, $ptrreg", LdStSTDU,
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[(set ptr_rc:$ea_res,
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(pre_store G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
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RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
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@ -681,7 +681,7 @@ def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
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[(set GPRC:$rD, (load iaddr:$src))]>;
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def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
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"lfs $rD, $src", LdStLFDU,
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"lfs $rD, $src", LdStLFD,
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[(set F4RC:$rD, (load iaddr:$src))]>;
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def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
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"lfd $rD, $src", LdStLFD,
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@ -691,32 +691,32 @@ def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
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// Unindexed (r+i) Loads with Update (preinc).
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let mayLoad = 1 in {
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def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
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"lbzu $rD, $addr", LdStLoad,
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"lbzu $rD, $addr", LdStLoadUpd,
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[]>, RegConstraint<"$addr.reg = $ea_result">,
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NoEncode<"$ea_result">;
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def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
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"lhau $rD, $addr", LdStLoad,
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"lhau $rD, $addr", LdStLHAU,
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[]>, RegConstraint<"$addr.reg = $ea_result">,
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NoEncode<"$ea_result">;
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def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
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"lhzu $rD, $addr", LdStLoad,
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"lhzu $rD, $addr", LdStLoadUpd,
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[]>, RegConstraint<"$addr.reg = $ea_result">,
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NoEncode<"$ea_result">;
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def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
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"lwzu $rD, $addr", LdStLoad,
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"lwzu $rD, $addr", LdStLoadUpd,
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[]>, RegConstraint<"$addr.reg = $ea_result">,
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NoEncode<"$ea_result">;
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def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
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"lfs $rD, $addr", LdStLFDU,
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"lfsu $rD, $addr", LdStLFDU,
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[]>, RegConstraint<"$addr.reg = $ea_result">,
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NoEncode<"$ea_result">;
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def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
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"lfd $rD, $addr", LdStLFD,
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"lfdu $rD, $addr", LdStLFDU,
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[]>, RegConstraint<"$addr.reg = $ea_result">,
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NoEncode<"$ea_result">;
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@ -724,37 +724,37 @@ def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
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// Indexed (r+r) Loads with Update (preinc).
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def LBZUX : XForm_1<31, 119, (outs GPRC:$rD, ptr_rc:$ea_result),
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(ins memrr:$addr),
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"lbzux $rD, $addr", LdStLoad,
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"lbzux $rD, $addr", LdStLoadUpd,
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[]>, RegConstraint<"$addr.offreg = $ea_result">,
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NoEncode<"$ea_result">;
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def LHAUX : XForm_1<31, 375, (outs GPRC:$rD, ptr_rc:$ea_result),
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(ins memrr:$addr),
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"lhaux $rD, $addr", LdStLoad,
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"lhaux $rD, $addr", LdStLHAU,
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[]>, RegConstraint<"$addr.offreg = $ea_result">,
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NoEncode<"$ea_result">;
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def LHZUX : XForm_1<31, 331, (outs GPRC:$rD, ptr_rc:$ea_result),
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(ins memrr:$addr),
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"lhzux $rD, $addr", LdStLoad,
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"lhzux $rD, $addr", LdStLoadUpd,
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[]>, RegConstraint<"$addr.offreg = $ea_result">,
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NoEncode<"$ea_result">;
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def LWZUX : XForm_1<31, 55, (outs GPRC:$rD, ptr_rc:$ea_result),
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(ins memrr:$addr),
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"lwzux $rD, $addr", LdStLoad,
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"lwzux $rD, $addr", LdStLoadUpd,
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[]>, RegConstraint<"$addr.offreg = $ea_result">,
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NoEncode<"$ea_result">;
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def LFSUX : XForm_1<31, 567, (outs F4RC:$rD, ptr_rc:$ea_result),
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(ins memrr:$addr),
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"lfsux $rD, $addr", LdStLoad,
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"lfsux $rD, $addr", LdStLFDU,
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[]>, RegConstraint<"$addr.offreg = $ea_result">,
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NoEncode<"$ea_result">;
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def LFDUX : XForm_1<31, 631, (outs F8RC:$rD, ptr_rc:$ea_result),
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(ins memrr:$addr),
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"lfdux $rD, $addr", LdStLoad,
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"lfdux $rD, $addr", LdStLFDU,
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[]>, RegConstraint<"$addr.offreg = $ea_result">,
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NoEncode<"$ea_result">;
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}
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@ -786,10 +786,10 @@ def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
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[(set GPRC:$rD, (PPClbrx xoaddr:$src, i32))]>;
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def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
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"lfsx $frD, $src", LdStLFDU,
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"lfsx $frD, $src", LdStLFD,
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[(set F4RC:$frD, (load xaddr:$src))]>;
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def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
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"lfdx $frD, $src", LdStLFDU,
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"lfdx $frD, $src", LdStLFD,
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[(set F8RC:$frD, (load xaddr:$src))]>;
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}
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@ -809,10 +809,10 @@ def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
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"stw $rS, $src", LdStStore,
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[(store GPRC:$rS, iaddr:$src)]>;
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def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
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"stfs $rS, $dst", LdStUX,
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"stfs $rS, $dst", LdStSTFD,
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[(store F4RC:$rS, iaddr:$dst)]>;
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def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
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"stfd $rS, $dst", LdStUX,
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"stfd $rS, $dst", LdStSTFD,
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[(store F8RC:$rS, iaddr:$dst)]>;
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}
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@ -820,33 +820,33 @@ def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
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let PPC970_Unit = 2 in {
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def STBU : DForm_1a<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
|
||||
symbolLo:$ptroff, ptr_rc:$ptrreg),
|
||||
"stbu $rS, $ptroff($ptrreg)", LdStStore,
|
||||
"stbu $rS, $ptroff($ptrreg)", LdStStoreUpd,
|
||||
[(set ptr_rc:$ea_res,
|
||||
(pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
|
||||
iaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
|
||||
def STHU : DForm_1a<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
|
||||
symbolLo:$ptroff, ptr_rc:$ptrreg),
|
||||
"sthu $rS, $ptroff($ptrreg)", LdStStore,
|
||||
"sthu $rS, $ptroff($ptrreg)", LdStStoreUpd,
|
||||
[(set ptr_rc:$ea_res,
|
||||
(pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
|
||||
iaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
|
||||
def STWU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
|
||||
symbolLo:$ptroff, ptr_rc:$ptrreg),
|
||||
"stwu $rS, $ptroff($ptrreg)", LdStStore,
|
||||
"stwu $rS, $ptroff($ptrreg)", LdStStoreUpd,
|
||||
[(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
|
||||
iaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
|
||||
def STFSU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
|
||||
symbolLo:$ptroff, ptr_rc:$ptrreg),
|
||||
"stfsu $rS, $ptroff($ptrreg)", LdStStore,
|
||||
"stfsu $rS, $ptroff($ptrreg)", LdStSTFDU,
|
||||
[(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
|
||||
iaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
|
||||
def STFDU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
|
||||
symbolLo:$ptroff, ptr_rc:$ptrreg),
|
||||
"stfdu $rS, $ptroff($ptrreg)", LdStStore,
|
||||
"stfdu $rS, $ptroff($ptrreg)", LdStSTFDU,
|
||||
[(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
|
||||
iaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
|
||||
@ -871,7 +871,7 @@ def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
|
||||
|
||||
def STBUX : XForm_8<31, 247, (outs ptr_rc:$ea_res),
|
||||
(ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
|
||||
"stbux $rS, $ptroff, $ptrreg", LdStStore,
|
||||
"stbux $rS, $ptroff, $ptrreg", LdStStoreUpd,
|
||||
[(set ptr_rc:$ea_res,
|
||||
(pre_truncsti8 GPRC:$rS,
|
||||
ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
|
||||
@ -880,7 +880,7 @@ def STBUX : XForm_8<31, 247, (outs ptr_rc:$ea_res),
|
||||
|
||||
def STHUX : XForm_8<31, 439, (outs ptr_rc:$ea_res),
|
||||
(ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
|
||||
"sthux $rS, $ptroff, $ptrreg", LdStStore,
|
||||
"sthux $rS, $ptroff, $ptrreg", LdStStoreUpd,
|
||||
[(set ptr_rc:$ea_res,
|
||||
(pre_truncsti16 GPRC:$rS,
|
||||
ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
|
||||
@ -889,7 +889,7 @@ def STHUX : XForm_8<31, 439, (outs ptr_rc:$ea_res),
|
||||
|
||||
def STWUX : XForm_8<31, 183, (outs ptr_rc:$ea_res),
|
||||
(ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
|
||||
"stwux $rS, $ptroff, $ptrreg", LdStStore,
|
||||
"stwux $rS, $ptroff, $ptrreg", LdStStoreUpd,
|
||||
[(set ptr_rc:$ea_res,
|
||||
(pre_store GPRC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
|
||||
@ -897,7 +897,7 @@ def STWUX : XForm_8<31, 183, (outs ptr_rc:$ea_res),
|
||||
|
||||
def STFSUX : XForm_8<31, 695, (outs ptr_rc:$ea_res),
|
||||
(ins F4RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
|
||||
"stfsux $rS, $ptroff, $ptrreg", LdStStore,
|
||||
"stfsux $rS, $ptroff, $ptrreg", LdStSTFDU,
|
||||
[(set ptr_rc:$ea_res,
|
||||
(pre_store F4RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
|
||||
@ -905,7 +905,7 @@ def STFSUX : XForm_8<31, 695, (outs ptr_rc:$ea_res),
|
||||
|
||||
def STFDUX : XForm_8<31, 759, (outs ptr_rc:$ea_res),
|
||||
(ins F8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
|
||||
"stfdux $rS, $ptroff, $ptrreg", LdStStore,
|
||||
"stfdux $rS, $ptroff, $ptrreg", LdStSTFDU,
|
||||
[(set ptr_rc:$ea_res,
|
||||
(pre_store F8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
|
||||
RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
|
||||
@ -921,14 +921,14 @@ def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
|
||||
PPC970_DGroup_Cracked;
|
||||
|
||||
def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
|
||||
"stfiwx $frS, $dst", LdStUX,
|
||||
"stfiwx $frS, $dst", LdStSTFD,
|
||||
[(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
|
||||
|
||||
def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
|
||||
"stfsx $frS, $dst", LdStUX,
|
||||
"stfsx $frS, $dst", LdStSTFD,
|
||||
[(store F4RC:$frS, xaddr:$dst)]>;
|
||||
def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
|
||||
"stfdx $frS, $dst", LdStUX,
|
||||
"stfdx $frS, $dst", LdStSTFD,
|
||||
[(store F8RC:$frS, xaddr:$dst)]>;
|
||||
}
|
||||
|
||||
@ -1251,7 +1251,7 @@ let Uses = [RM] in {
|
||||
PPC970_DGroup_Single, PPC970_Unit_FPU;
|
||||
def FADDrtz: AForm_2<63, 21,
|
||||
(outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
|
||||
"fadd $FRT, $FRA, $FRB", FPGeneral,
|
||||
"fadd $FRT, $FRA, $FRB", FPAddSub,
|
||||
[(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>,
|
||||
PPC970_DGroup_Single, PPC970_Unit_FPU;
|
||||
}
|
||||
@ -1382,7 +1382,7 @@ def FSELS : AForm_1<63, 23,
|
||||
let Uses = [RM] in {
|
||||
def FADD : AForm_2<63, 21,
|
||||
(outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
|
||||
"fadd $FRT, $FRA, $FRB", FPGeneral,
|
||||
"fadd $FRT, $FRA, $FRB", FPAddSub,
|
||||
[(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
|
||||
def FADDS : AForm_2<59, 21,
|
||||
(outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
|
||||
@ -1406,7 +1406,7 @@ let Uses = [RM] in {
|
||||
[(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
|
||||
def FSUB : AForm_2<63, 20,
|
||||
(outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
|
||||
"fsub $FRT, $FRA, $FRB", FPGeneral,
|
||||
"fsub $FRT, $FRA, $FRB", FPAddSub,
|
||||
[(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
|
||||
def FSUBS : AForm_2<59, 20,
|
||||
(outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
|
||||
|
||||
@ -40,6 +40,7 @@ def IntMulHWU : InstrItinClass;
|
||||
def IntMulLI : InstrItinClass;
|
||||
def IntRFID : InstrItinClass;
|
||||
def IntRotateD : InstrItinClass;
|
||||
def IntRotateDI : InstrItinClass;
|
||||
def IntRotate : InstrItinClass;
|
||||
def IntShift : InstrItinClass;
|
||||
def IntTrapD : InstrItinClass;
|
||||
@ -52,15 +53,18 @@ def LdStDCBA : InstrItinClass;
|
||||
def LdStDCBF : InstrItinClass;
|
||||
def LdStDCBI : InstrItinClass;
|
||||
def LdStLoad : InstrItinClass;
|
||||
def LdStLoadUpd : InstrItinClass;
|
||||
def LdStStore : InstrItinClass;
|
||||
def LdStStoreUpd : InstrItinClass;
|
||||
def LdStDSS : InstrItinClass;
|
||||
def LdStICBI : InstrItinClass;
|
||||
def LdStUX : InstrItinClass;
|
||||
def LdStLD : InstrItinClass;
|
||||
def LdStLDU : InstrItinClass;
|
||||
def LdStLDARX : InstrItinClass;
|
||||
def LdStLFD : InstrItinClass;
|
||||
def LdStLFDU : InstrItinClass;
|
||||
def LdStLHA : InstrItinClass;
|
||||
def LdStLHAU : InstrItinClass;
|
||||
def LdStLMW : InstrItinClass;
|
||||
def LdStLVecX : InstrItinClass;
|
||||
def LdStLWA : InstrItinClass;
|
||||
@ -69,6 +73,9 @@ def LdStSLBIA : InstrItinClass;
|
||||
def LdStSLBIE : InstrItinClass;
|
||||
def LdStSTD : InstrItinClass;
|
||||
def LdStSTDCX : InstrItinClass;
|
||||
def LdStSTDU : InstrItinClass;
|
||||
def LdStSTFD : InstrItinClass;
|
||||
def LdStSTFDU : InstrItinClass;
|
||||
def LdStSTVEBX : InstrItinClass;
|
||||
def LdStSTWCX : InstrItinClass;
|
||||
def LdStSync : InstrItinClass;
|
||||
@ -86,6 +93,7 @@ def SprMTSRIN : InstrItinClass;
|
||||
def SprRFI : InstrItinClass;
|
||||
def SprSC : InstrItinClass;
|
||||
def FPGeneral : InstrItinClass;
|
||||
def FPAddSub : InstrItinClass;
|
||||
def FPCompare : InstrItinClass;
|
||||
def FPDivD : InstrItinClass;
|
||||
def FPDivS : InstrItinClass;
|
||||
@ -171,7 +179,7 @@ include "PPCScheduleA2.td"
|
||||
// extsh IntSimple
|
||||
// extsw IntSimple
|
||||
// fabs FPGeneral
|
||||
// fadd FPGeneral
|
||||
// fadd FPAddSub
|
||||
// fadds FPGeneral
|
||||
// fcfid FPGeneral
|
||||
// fcmpo FPCompare
|
||||
@ -201,35 +209,35 @@ include "PPCScheduleA2.td"
|
||||
// fsel FPGeneral
|
||||
// fsqrt FPSqrt
|
||||
// fsqrts FPSqrt
|
||||
// fsub FPGeneral
|
||||
// fsub FPAddSub
|
||||
// fsubs FPGeneral
|
||||
// icbi LdStICBI
|
||||
// isync SprISYNC
|
||||
// lbz LdStLoad
|
||||
// lbzu LdStLoad
|
||||
// lbzux LdStUX
|
||||
// lbzu LdStLoadUpd
|
||||
// lbzux LdStLoadUpd
|
||||
// lbzx LdStLoad
|
||||
// ld LdStLD
|
||||
// ldarx LdStLDARX
|
||||
// ldu LdStLD
|
||||
// ldux LdStLD
|
||||
// ldu LdStLDU
|
||||
// ldux LdStLDU
|
||||
// ldx LdStLD
|
||||
// lfd LdStLFD
|
||||
// lfdu LdStLFDU
|
||||
// lfdux LdStLFDU
|
||||
// lfdx LdStLFDU
|
||||
// lfs LdStLFDU
|
||||
// lfdx LdStLFD
|
||||
// lfs LdStLFD
|
||||
// lfsu LdStLFDU
|
||||
// lfsux LdStLFDU
|
||||
// lfsx LdStLFDU
|
||||
// lfsx LdStLFD
|
||||
// lha LdStLHA
|
||||
// lhau LdStLHA
|
||||
// lhaux LdStLHA
|
||||
// lhau LdStLHAU
|
||||
// lhaux LdStLHAU
|
||||
// lhax LdStLHA
|
||||
// lhbrx LdStLoad
|
||||
// lhz LdStLoad
|
||||
// lhzu LdStLoad
|
||||
// lhzux LdStUX
|
||||
// lhzu LdStLoadUpd
|
||||
// lhzux LdStLoadUpd
|
||||
// lhzx LdStLoad
|
||||
// lmw LdStLMW
|
||||
// lswi LdStLMW
|
||||
@ -243,12 +251,12 @@ include "PPCScheduleA2.td"
|
||||
// lvxl LdStLVecX
|
||||
// lwa LdStLWA
|
||||
// lwarx LdStLWARX
|
||||
// lwaux LdStLHA
|
||||
// lwaux LdStLHAU
|
||||
// lwax LdStLHA
|
||||
// lwbrx LdStLoad
|
||||
// lwz LdStLoad
|
||||
// lwzu LdStLoad
|
||||
// lwzux LdStUX
|
||||
// lwzu LdStLoadUpd
|
||||
// lwzux LdStLoadUpd
|
||||
// lwzx LdStLoad
|
||||
// mcrf BrMCR
|
||||
// mcrfs FPGeneral
|
||||
@ -292,10 +300,10 @@ include "PPCScheduleA2.td"
|
||||
// rfid IntRFID
|
||||
// rldcl IntRotateD
|
||||
// rldcr IntRotateD
|
||||
// rldic IntRotateD
|
||||
// rldicl IntRotateD
|
||||
// rldicr IntRotateD
|
||||
// rldimi IntRotateD
|
||||
// rldic IntRotateDI
|
||||
// rldicl IntRotateDI
|
||||
// rldicr IntRotateDI
|
||||
// rldimi IntRotateDI
|
||||
// rlwimi IntRotate
|
||||
// rlwinm IntGeneral
|
||||
// rlwnm IntGeneral
|
||||
@ -305,33 +313,33 @@ include "PPCScheduleA2.td"
|
||||
// sld IntRotateD
|
||||
// slw IntGeneral
|
||||
// srad IntRotateD
|
||||
// sradi IntRotateD
|
||||
// sradi IntRotateDI
|
||||
// sraw IntShift
|
||||
// srawi IntShift
|
||||
// srd IntRotateD
|
||||
// srw IntGeneral
|
||||
// stb LdStStore
|
||||
// stbu LdStStore
|
||||
// stbux LdStStore
|
||||
// stbu LdStStoreUpd
|
||||
// stbux LdStStoreUpd
|
||||
// stbx LdStStore
|
||||
// std LdStSTD
|
||||
// stdcx. LdStSTDCX
|
||||
// stdu LdStSTD
|
||||
// stdux LdStSTD
|
||||
// stdu LdStSTDU
|
||||
// stdux LdStSTDU
|
||||
// stdx LdStSTD
|
||||
// stfd LdStUX
|
||||
// stfdu LdStUX
|
||||
// stfdux LdStUX
|
||||
// stfdx LdStUX
|
||||
// stfiwx LdStUX
|
||||
// stfs LdStUX
|
||||
// stfsu LdStUX
|
||||
// stfsux LdStUX
|
||||
// stfsx LdStUX
|
||||
// stfd LdStSTFD
|
||||
// stfdu LdStSTFDU
|
||||
// stfdux LdStSTFDU
|
||||
// stfdx LdStSTFD
|
||||
// stfiwx LdStSTFD
|
||||
// stfs LdStSTFD
|
||||
// stfsu LdStSTFDU
|
||||
// stfsux LdStSTFDU
|
||||
// stfsx LdStSTFD
|
||||
// sth LdStStore
|
||||
// sthbrx LdStStore
|
||||
// sthu LdStStore
|
||||
// sthux LdStStore
|
||||
// sthu LdStStoreUpd
|
||||
// sthux LdStStoreUpd
|
||||
// sthx LdStStore
|
||||
// stmw LdStLMW
|
||||
// stswi LdStLMW
|
||||
@ -344,8 +352,8 @@ include "PPCScheduleA2.td"
|
||||
// stw LdStStore
|
||||
// stwbrx LdStStore
|
||||
// stwcx. LdStSTWCX
|
||||
// stwu LdStStore
|
||||
// stwux LdStStore
|
||||
// stwu LdStStoreUpd
|
||||
// stwux LdStStoreUpd
|
||||
// stwx LdStStore
|
||||
// subf IntGeneral
|
||||
// subfc IntGeneral
|
||||
|
||||
@ -288,6 +288,15 @@ def PPC440Itineraries : ProcessorItineraries<
|
||||
InstrStage<2, [LWB]>],
|
||||
[9, 5],
|
||||
[GPR_Bypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStLoadUpd , [InstrStage<1, [IFTH1, IFTH2]>,
|
||||
InstrStage<1, [PDCD1, PDCD2]>,
|
||||
InstrStage<1, [DISS1, DISS2]>,
|
||||
InstrStage<1, [LRACC]>,
|
||||
InstrStage<1, [AGEN]>,
|
||||
InstrStage<1, [CRD]>,
|
||||
InstrStage<2, [LWB]>],
|
||||
[9, 5],
|
||||
[GPR_Bypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStStore , [InstrStage<1, [IFTH1, IFTH2]>,
|
||||
InstrStage<1, [PDCD1, PDCD2]>,
|
||||
InstrStage<1, [DISS1, DISS2]>,
|
||||
@ -297,6 +306,15 @@ def PPC440Itineraries : ProcessorItineraries<
|
||||
InstrStage<2, [LWB]>],
|
||||
[8, 5],
|
||||
[NoBypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStStoreUpd, [InstrStage<1, [IFTH1, IFTH2]>,
|
||||
InstrStage<1, [PDCD1, PDCD2]>,
|
||||
InstrStage<1, [DISS1, DISS2]>,
|
||||
InstrStage<1, [LRACC]>,
|
||||
InstrStage<1, [AGEN]>,
|
||||
InstrStage<1, [CRD]>,
|
||||
InstrStage<2, [LWB]>],
|
||||
[8, 5],
|
||||
[NoBypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStICBI , [InstrStage<1, [IFTH1, IFTH2]>,
|
||||
InstrStage<1, [PDCD1, PDCD2]>,
|
||||
InstrStage<1, [DISS1, DISS2]>,
|
||||
@ -306,7 +324,7 @@ def PPC440Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [LWB]>],
|
||||
[8, 5],
|
||||
[NoBypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStUX , [InstrStage<1, [IFTH1, IFTH2]>,
|
||||
InstrItinData<LdStSTFD , [InstrStage<1, [IFTH1, IFTH2]>,
|
||||
InstrStage<1, [PDCD1, PDCD2]>,
|
||||
InstrStage<1, [DISS1, DISS2]>,
|
||||
InstrStage<1, [LRACC]>,
|
||||
@ -315,6 +333,15 @@ def PPC440Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [LWB]>],
|
||||
[8, 5, 5],
|
||||
[NoBypass, GPR_Bypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStSTFDU , [InstrStage<1, [IFTH1, IFTH2]>,
|
||||
InstrStage<1, [PDCD1, PDCD2]>,
|
||||
InstrStage<1, [DISS1, DISS2]>,
|
||||
InstrStage<1, [LRACC]>,
|
||||
InstrStage<1, [AGEN]>,
|
||||
InstrStage<1, [CRD]>,
|
||||
InstrStage<1, [LWB]>],
|
||||
[8, 5, 5],
|
||||
[NoBypass, GPR_Bypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStLFD , [InstrStage<1, [IFTH1, IFTH2]>,
|
||||
InstrStage<1, [PDCD1, PDCD2]>,
|
||||
InstrStage<1, [DISS1, DISS2]>,
|
||||
@ -342,6 +369,15 @@ def PPC440Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [LWB]>],
|
||||
[8, 5],
|
||||
[NoBypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStLHAU , [InstrStage<1, [IFTH1, IFTH2]>,
|
||||
InstrStage<1, [PDCD1, PDCD2]>,
|
||||
InstrStage<1, [DISS1, DISS2]>,
|
||||
InstrStage<1, [LRACC]>,
|
||||
InstrStage<1, [AGEN]>,
|
||||
InstrStage<1, [CRD]>,
|
||||
InstrStage<1, [LWB]>],
|
||||
[8, 5],
|
||||
[NoBypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStLMW , [InstrStage<1, [IFTH1, IFTH2]>,
|
||||
InstrStage<1, [PDCD1, PDCD2]>,
|
||||
InstrStage<1, [DISS1, DISS2]>,
|
||||
@ -371,6 +407,15 @@ def PPC440Itineraries : ProcessorItineraries<
|
||||
InstrStage<2, [LWB]>],
|
||||
[8, 5],
|
||||
[NoBypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStSTDU , [InstrStage<1, [IFTH1, IFTH2]>,
|
||||
InstrStage<1, [PDCD1, PDCD2]>,
|
||||
InstrStage<1, [DISS1, DISS2]>,
|
||||
InstrStage<1, [LRACC]>,
|
||||
InstrStage<1, [AGEN]>,
|
||||
InstrStage<1, [CRD]>,
|
||||
InstrStage<2, [LWB]>],
|
||||
[8, 5],
|
||||
[NoBypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStSTDCX , [InstrStage<1, [IFTH1, IFTH2]>,
|
||||
InstrStage<1, [PDCD1, PDCD2]>,
|
||||
InstrStage<1, [DISS1]>,
|
||||
@ -537,6 +582,19 @@ def PPC440Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [FWB]>],
|
||||
[10, 4, 4],
|
||||
[FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
|
||||
InstrItinData<FPAddSub , [InstrStage<1, [IFTH1, IFTH2]>,
|
||||
InstrStage<1, [PDCD1, PDCD2]>,
|
||||
InstrStage<1, [DISS1, DISS2]>,
|
||||
InstrStage<1, [FRACC]>,
|
||||
InstrStage<1, [FEXE1]>,
|
||||
InstrStage<1, [FEXE2]>,
|
||||
InstrStage<1, [FEXE3]>,
|
||||
InstrStage<1, [FEXE4]>,
|
||||
InstrStage<1, [FEXE5]>,
|
||||
InstrStage<1, [FEXE6]>,
|
||||
InstrStage<1, [FWB]>],
|
||||
[10, 4, 4],
|
||||
[FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
|
||||
InstrItinData<FPCompare , [InstrStage<1, [IFTH1, IFTH2]>,
|
||||
InstrStage<1, [PDCD1, PDCD2]>,
|
||||
InstrStage<1, [DISS1, DISS2]>,
|
||||
|
||||
@ -181,6 +181,17 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[10, 7, 7],
|
||||
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
|
||||
InstrItinData<IntRotateDI , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||||
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||||
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[10, 7, 7],
|
||||
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
|
||||
InstrItinData<IntShift , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
@ -302,7 +313,18 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[14, 7],
|
||||
[GPR_Bypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStLD , [InstrStage<4,
|
||||
InstrItinData<LdStLoadUpd , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||||
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||||
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[14, 7],
|
||||
[GPR_Bypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStLDU , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
@ -324,6 +346,17 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[13, 7],
|
||||
[GPR_Bypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStStoreUpd, [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||||
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||||
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[13, 7],
|
||||
[GPR_Bypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStICBI , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
@ -335,7 +368,7 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[14, 7],
|
||||
[NoBypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStUX , [InstrStage<4,
|
||||
InstrItinData<LdStSTFD , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
@ -346,6 +379,17 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[14, 7, 7],
|
||||
[NoBypass, FPR_Bypass, FPR_Bypass]>,
|
||||
InstrItinData<LdStSTFDU , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||||
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||||
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[14, 7, 7],
|
||||
[NoBypass, FPR_Bypass, FPR_Bypass]>,
|
||||
InstrItinData<LdStLFD , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
@ -379,6 +423,17 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[14, 7],
|
||||
[NoBypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStLHAU , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||||
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||||
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[14, 7],
|
||||
[NoBypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStLMW , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
@ -412,6 +467,17 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[13, 7],
|
||||
[GPR_Bypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStSTDU , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
|
||||
InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
|
||||
InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
|
||||
InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
|
||||
[13, 7],
|
||||
[GPR_Bypass, GPR_Bypass]>,
|
||||
InstrItinData<LdStSTDCX , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
@ -593,6 +659,17 @@ def PPCA2Itineraries : ProcessorItineraries<
|
||||
InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
|
||||
[15, 7, 7],
|
||||
[FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
|
||||
InstrItinData<FPAddSub , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
IU4_4, IU4_5, IU4_6, IU4_7]>,
|
||||
InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
|
||||
InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>,
|
||||
InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>,
|
||||
InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>,
|
||||
InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
|
||||
[15, 7, 7],
|
||||
[FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
|
||||
InstrItinData<FPCompare , [InstrStage<4,
|
||||
[IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
|
||||
InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
|
||||
|
||||
@ -34,12 +34,16 @@ def G3Itineraries : ProcessorItineraries<
|
||||
InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStLoad , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStLoadUpd , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStStore , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStStoreUpd, [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStICBI , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStUX , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStSTFD , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStSTFDU , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStLFD , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStLFDU , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStLHA , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStLHAU , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStLMW , [InstrStage<34, [SLU]>]>,
|
||||
InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStSTWCX , [InstrStage<8, [SLU]>]>,
|
||||
@ -58,6 +62,7 @@ def G3Itineraries : ProcessorItineraries<
|
||||
InstrItinData<SprRFI , [InstrStage<2, [SRU]>]>,
|
||||
InstrItinData<SprSC , [InstrStage<2, [SRU]>]>,
|
||||
InstrItinData<FPGeneral , [InstrStage<1, [FPU1]>]>,
|
||||
InstrItinData<FPAddSub , [InstrStage<1, [FPU1]>]>,
|
||||
InstrItinData<FPCompare , [InstrStage<1, [FPU1]>]>,
|
||||
InstrItinData<FPDivD , [InstrStage<31, [FPU1]>]>,
|
||||
InstrItinData<FPDivS , [InstrStage<17, [FPU1]>]>,
|
||||
|
||||
@ -33,13 +33,17 @@ def G4Itineraries : ProcessorItineraries<
|
||||
InstrItinData<LdStDCBF , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStDCBI , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStLoad , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStLoadUpd , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStStore , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStStoreUpd, [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStDSS , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStICBI , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStUX , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStSTFD , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStSTFDU , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStLFD , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStLFDU , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStLHA , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStLHAU , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStLMW , [InstrStage<34, [SLU]>]>,
|
||||
InstrItinData<LdStLVecX , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>,
|
||||
@ -60,6 +64,7 @@ def G4Itineraries : ProcessorItineraries<
|
||||
InstrItinData<SprRFI , [InstrStage<2, [SRU]>]>,
|
||||
InstrItinData<SprSC , [InstrStage<2, [SRU]>]>,
|
||||
InstrItinData<FPGeneral , [InstrStage<1, [FPU1]>]>,
|
||||
InstrItinData<FPAddSub , [InstrStage<1, [FPU1]>]>,
|
||||
InstrItinData<FPCompare , [InstrStage<1, [FPU1]>]>,
|
||||
InstrItinData<FPDivD , [InstrStage<31, [FPU1]>]>,
|
||||
InstrItinData<FPDivS , [InstrStage<17, [FPU1]>]>,
|
||||
|
||||
@ -36,19 +36,24 @@ def G4PlusItineraries : ProcessorItineraries<
|
||||
InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStLoad , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStLoadUpd , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStStore , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStStoreUpd, [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStDSS , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStICBI , [InstrStage<3, [IU2]>]>,
|
||||
InstrItinData<LdStUX , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStSTFD , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStSTFDU , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStLFD , [InstrStage<4, [SLU]>]>,
|
||||
InstrItinData<LdStLFDU , [InstrStage<4, [SLU]>]>,
|
||||
InstrItinData<LdStLHA , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStLHAU , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStLMW , [InstrStage<37, [SLU]>]>,
|
||||
InstrItinData<LdStLVecX , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStLWA , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStSTD , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStSTDCX , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStSTDU , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStSTVEBX , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStSTWCX , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStSync , [InstrStage<35, [SLU]>]>,
|
||||
@ -66,6 +71,7 @@ def G4PlusItineraries : ProcessorItineraries<
|
||||
InstrItinData<SprRFI , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
|
||||
InstrItinData<SprSC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>,
|
||||
InstrItinData<FPGeneral , [InstrStage<5, [FPU1]>]>,
|
||||
InstrItinData<FPAddSub , [InstrStage<5, [FPU1]>]>,
|
||||
InstrItinData<FPCompare , [InstrStage<5, [FPU1]>]>,
|
||||
InstrItinData<FPDivD , [InstrStage<35, [FPU1]>]>,
|
||||
InstrItinData<FPDivS , [InstrStage<21, [FPU1]>]>,
|
||||
|
||||
@ -27,6 +27,7 @@ def G5Itineraries : ProcessorItineraries<
|
||||
InstrItinData<IntMulLI , [InstrStage<4, [IU1, IU2]>]>,
|
||||
InstrItinData<IntRFID , [InstrStage<1, [IU2]>]>,
|
||||
InstrItinData<IntRotateD , [InstrStage<2, [IU1, IU2]>]>,
|
||||
InstrItinData<IntRotateDI , [InstrStage<2, [IU1, IU2]>]>,
|
||||
InstrItinData<IntRotate , [InstrStage<4, [IU1, IU2]>]>,
|
||||
InstrItinData<IntShift , [InstrStage<2, [IU1, IU2]>]>,
|
||||
InstrItinData<IntTrapD , [InstrStage<1, [IU1, IU2]>]>,
|
||||
@ -37,15 +38,20 @@ def G5Itineraries : ProcessorItineraries<
|
||||
InstrItinData<BrMCRX , [InstrStage<3, [BPU]>]>,
|
||||
InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStLoad , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStLoadUpd , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStStore , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStStoreUpd, [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStDSS , [InstrStage<10, [SLU]>]>,
|
||||
InstrItinData<LdStICBI , [InstrStage<40, [SLU]>]>,
|
||||
InstrItinData<LdStUX , [InstrStage<4, [SLU]>]>,
|
||||
InstrItinData<LdStSTFD , [InstrStage<4, [SLU]>]>,
|
||||
InstrItinData<LdStSTFDU , [InstrStage<4, [SLU]>]>,
|
||||
InstrItinData<LdStLD , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStLDU , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStLDARX , [InstrStage<11, [SLU]>]>,
|
||||
InstrItinData<LdStLFD , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStLFDU , [InstrStage<5, [SLU]>]>,
|
||||
InstrItinData<LdStLHA , [InstrStage<5, [SLU]>]>,
|
||||
InstrItinData<LdStLHAU , [InstrStage<5, [SLU]>]>,
|
||||
InstrItinData<LdStLMW , [InstrStage<64, [SLU]>]>,
|
||||
InstrItinData<LdStLVecX , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStLWA , [InstrStage<5, [SLU]>]>,
|
||||
@ -53,6 +59,7 @@ def G5Itineraries : ProcessorItineraries<
|
||||
InstrItinData<LdStSLBIA , [InstrStage<40, [SLU]>]>, // needs work
|
||||
InstrItinData<LdStSLBIE , [InstrStage<2, [SLU]>]>,
|
||||
InstrItinData<LdStSTD , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStSTDU , [InstrStage<3, [SLU]>]>,
|
||||
InstrItinData<LdStSTDCX , [InstrStage<11, [SLU]>]>,
|
||||
InstrItinData<LdStSTVEBX , [InstrStage<5, [SLU]>]>,
|
||||
InstrItinData<LdStSTWCX , [InstrStage<11, [SLU]>]>,
|
||||
@ -69,6 +76,7 @@ def G5Itineraries : ProcessorItineraries<
|
||||
InstrItinData<SprMTSPR , [InstrStage<8, [IU2]>]>,
|
||||
InstrItinData<SprSC , [InstrStage<1, [IU2]>]>,
|
||||
InstrItinData<FPGeneral , [InstrStage<6, [FPU1, FPU2]>]>,
|
||||
InstrItinData<FPAddSub , [InstrStage<6, [FPU1, FPU2]>]>,
|
||||
InstrItinData<FPCompare , [InstrStage<8, [FPU1, FPU2]>]>,
|
||||
InstrItinData<FPDivD , [InstrStage<33, [FPU1, FPU2]>]>,
|
||||
InstrItinData<FPDivS , [InstrStage<33, [FPU1, FPU2]>]>,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user