From 8dd37f7b7dca7907f9f070dc96359f242e102163 Mon Sep 17 00:00:00 2001 From: Bruno Cardoso Lopes Date: Thu, 20 Jan 2011 18:32:09 +0000 Subject: [PATCH] Add cdp/cdp2 instructions for thumb/thumb2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123929 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrThumb.td | 25 +++++++++++++++++++++++ lib/Target/ARM/ARMInstrThumb2.td | 25 +++++++++++++++++++++++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 2 +- test/MC/ARM/thumb.s | 3 +++ test/MC/ARM/thumb2.s | 3 +++ 5 files changed, 57 insertions(+), 1 deletion(-) diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 406d8db792a..6dc07eb7b67 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -1377,6 +1377,31 @@ class tMovRRCopro def tMCRR : tMovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>; def tMRRC : tMovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>; +//===----------------------------------------------------------------------===// +// Other Coprocessor Instructions. For disassembly only. +// +def tCDP : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, + c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2), + "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", + [/* For disassembly only; pattern left blank */]> { + let Inst{27-24} = 0b1110; + + bits<4> opc1; + bits<4> CRn; + bits<4> CRd; + bits<4> cop; + bits<3> opc2; + bits<4> CRm; + + let Inst{3-0} = CRm; + let Inst{4} = 0; + let Inst{7-5} = opc2; + let Inst{11-8} = cop; + let Inst{15-12} = CRd; + let Inst{19-16} = CRn; + let Inst{23-20} = opc1; +} + //===----------------------------------------------------------------------===// // TLS Instructions // diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 8fb5eeb92fa..7cac5693214 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -3378,3 +3378,28 @@ class t2MovRRCopro def t2MCRR : t2MovRRCopro<"mcrr2",0/* from ARM core register to coprocessor */>; def t2MRRC : t2MovRRCopro<"mrrc2",1/* from coprocessor to ARM core register */>; +//===----------------------------------------------------------------------===// +// Other Coprocessor Instructions. For disassembly only. +// + +def t2CDP2 : T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, + c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2), + "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", + [/* For disassembly only; pattern left blank */]> { + let Inst{27-24} = 0b1110; + + bits<4> opc1; + bits<4> CRn; + bits<4> CRd; + bits<4> cop; + bits<3> opc2; + bits<4> CRm; + + let Inst{3-0} = CRm; + let Inst{4} = 0; + let Inst{7-5} = opc2; + let Inst{11-8} = cop; + let Inst{15-12} = CRd; + let Inst{19-16} = CRn; + let Inst{23-20} = opc1; +} diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index a10e1581050..ee6ef2b8192 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -1202,7 +1202,7 @@ GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, if (isThumb) if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || - Mnemonic == "mrc" || Mnemonic == "mrrc") + Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp") CanAcceptPredicationCode = false; } diff --git a/test/MC/ARM/thumb.s b/test/MC/ARM/thumb.s index f1af26ca9ed..21052576c14 100644 --- a/test/MC/ARM/thumb.s +++ b/test/MC/ARM/thumb.s @@ -51,3 +51,6 @@ @ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x54,0xec,0x11,0x57] mrrc p7, #1, r5, r4, c1 +@ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x11,0xee,0x81,0x17] + cdp p7, #1, c1, c1, c1, #4 + diff --git a/test/MC/ARM/thumb2.s b/test/MC/ARM/thumb2.s index a62b086c9ef..46bd37fbab0 100644 --- a/test/MC/ARM/thumb2.s +++ b/test/MC/ARM/thumb2.s @@ -194,3 +194,6 @@ @ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x54,0xfc,0x11,0x57] mrrc2 p7, #1, r5, r4, c1 +@ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x11,0xfe,0x81,0x17] + cdp2 p7, #1, c1, c1, c1, #4 +