6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-10-25 10:27:04 +00:00
Code Issues Projects Releases Wiki Activity

Drop support for Mips1 and Mips2.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139405 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
2011-09-09 20:45:50 +00:00
parent 8ffad56f8e
commit 8ddf6531b8
17 changed files with 16 additions and 167 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
lib/Target/Mips/MipsAsmPrinter.cpp
View File

@@ -36,7 +36,6 @@
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/Twine.h"
#include "llvm/Support/TargetRegistry.h"
@@ -56,23 +55,6 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
MipsMCInstLower MCInstLowering(Mang, *MF, *this);
unsigned Opc = MI->getOpcode();
// If target is Mips1, expand double precision load/store to two single
// precision loads/stores (and delay slot if MI is a load).
if (Subtarget->isMips1() && (Opc == Mips::LDC1 || Opc == Mips::SDC1)) {
SmallVector<MCInst, 4> MCInsts;
const unsigned* SubReg =
TM.getRegisterInfo()->getSubRegisters(MI->getOperand(0).getReg());
MCInstLowering.LowerMips1F64LoadStore(MI, Opc, MCInsts,
Subtarget->isLittle(), SubReg);
for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin();
I != MCInsts.end(); ++I)
OutStreamer.EmitInstruction(*I);
return;
}
MCInst TmpInst0;
MCInstLowering.Lower(MI, TmpInst0);