mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-19 04:32:19 +00:00
Stop using isTwoAddress, switching to operand constraints instead.
Tell the codegen emitter that specific operands are not to be encoded, fixing JIT regressions w.r.t. pre-inc loads and stores (e.g. lwzu, which we generate even when general preinc loads are not enabled). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31770 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
f64f9a4b75
commit
8e28b5c426
@ -246,11 +246,12 @@ def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
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[(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
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let isTwoAddress = 1, isCommutable = 1 in {
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let isCommutable = 1 in {
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def RLDIMI : MDForm_1<30, 3,
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(ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
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"rldimi $rA, $rS, $SH, $MB", IntRotateD,
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[]>, isPPC64;
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[]>, isPPC64, RegConstraint<"$rSi = $rA">,
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NoEncode<"$rSi">;
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}
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// Rotate instructions.
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@ -290,10 +291,11 @@ def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src),
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PPC970_DGroup_Cracked;
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// Update forms.
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def LHAU8 : DForm_1<43, (ops G8RC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
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def LHAU8 : DForm_1<43, (ops G8RC:$rD, ptr_rc:$ea_result, symbolLo:$disp,
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ptr_rc:$rA),
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"lhau $rD, $disp($rA)", LdStGeneral,
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[]>, RegConstraint<"$rA = $rA_result">;
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[]>, RegConstraint<"$rA = $ea_result">,
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NoEncode<"$ea_result">;
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// NO LWAU!
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}
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@ -324,14 +326,16 @@ def LWZX8 : XForm_1<31, 23, (ops G8RC:$rD, memrr:$src),
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// Update forms.
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def LBZU8 : DForm_1<35, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr),
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"lbzu $rD, $addr", LdStGeneral,
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[]>, RegConstraint<"$addr.reg = $ea_result">;
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[]>, RegConstraint<"$addr.reg = $ea_result">,
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NoEncode<"$ea_result">;
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def LHZU8 : DForm_1<41, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr),
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"lhzu $rD, $addr", LdStGeneral,
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[]>, RegConstraint<"$addr.reg = $ea_result">;
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[]>, RegConstraint<"$addr.reg = $ea_result">,
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NoEncode<"$ea_result">;
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def LWZU8 : DForm_1<33, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr),
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"lwzu $rD, $addr", LdStGeneral,
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[]>, RegConstraint<"$addr.reg = $ea_result">;
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[]>, RegConstraint<"$addr.reg = $ea_result">,
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NoEncode<"$ea_result">;
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}
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@ -346,7 +350,8 @@ def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src),
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def LDU : DSForm_1<58, 1, (ops G8RC:$rD, ptr_rc:$ea_result, memrix:$addr),
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"ldu $rD, $addr", LdStLD,
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[]>, RegConstraint<"$addr.reg = $ea_result">, isPPC64;
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[]>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
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NoEncode<"$ea_result">;
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}
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@ -378,13 +383,13 @@ def STDX_32 : XForm_8<31, 149, (ops GPRC:$rT, memrr:$dst),
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// Truncating stores.
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def STB8 : DForm_3<38, (ops G8RC:$rS, memri:$src),
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def STB8 : DForm_1<38, (ops G8RC:$rS, memri:$src),
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"stb $rS, $src", LdStGeneral,
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[(truncstorei8 G8RC:$rS, iaddr:$src)]>;
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def STH8 : DForm_3<44, (ops G8RC:$rS, memri:$src),
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def STH8 : DForm_1<44, (ops G8RC:$rS, memri:$src),
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"sth $rS, $src", LdStGeneral,
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[(truncstorei16 G8RC:$rS, iaddr:$src)]>;
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def STW8 : DForm_3<36, (ops G8RC:$rS, memri:$src),
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def STW8 : DForm_1<36, (ops G8RC:$rS, memri:$src),
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"stw $rS, $src", LdStGeneral,
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[(truncstorei32 G8RC:$rS, iaddr:$src)]>;
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def STBX8 : XForm_8<31, 215, (ops G8RC:$rS, memrr:$dst),
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@ -120,11 +120,6 @@ class DForm_2_r0<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
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let Inst{16-31} = B;
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}
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// Currently we make the use/def reg distinction in ISel, not tablegen
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class DForm_3<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: DForm_1<opcode, OL, asmstr, itin, pattern>;
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class DForm_4<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: I<opcode, OL, asmstr, itin> {
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@ -200,6 +200,9 @@ class isDOT {
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class RegConstraint<string C> {
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string Constraints = C;
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}
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class NoEncode<string E> {
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string DisableEncoding = E;
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}
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//===----------------------------------------------------------------------===//
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@ -438,26 +441,33 @@ def LFD : DForm_1<50, (ops F8RC:$rD, memri:$src),
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// Unindexed (r+i) Loads with Update (preinc).
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def LBZU : DForm_1<35, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
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"lbzu $rD, $addr", LdStGeneral,
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[]>, RegConstraint<"$addr.reg = $ea_result">;
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[]>, RegConstraint<"$addr.reg = $ea_result">,
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NoEncode<"$ea_result">;
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def LHAU : DForm_1<43, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
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"lhau $rD, $addr", LdStGeneral,
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[]>, RegConstraint<"$addr.reg = $ea_result">;
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[]>, RegConstraint<"$addr.reg = $ea_result">,
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NoEncode<"$ea_result">;
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def LHZU : DForm_1<41, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
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"lhzu $rD, $addr", LdStGeneral,
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[]>, RegConstraint<"$addr.reg = $ea_result">;
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[]>, RegConstraint<"$addr.reg = $ea_result">,
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NoEncode<"$ea_result">;
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def LWZU : DForm_1<33, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
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"lwzu $rD, $addr", LdStGeneral,
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[]>, RegConstraint<"$addr.reg = $ea_result">;
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[]>, RegConstraint<"$addr.reg = $ea_result">,
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NoEncode<"$ea_result">;
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def LFSU : DForm_1<49, (ops F4RC:$rD, ptr_rc:$ea_result, memri:$addr),
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"lfs $rD, $addr", LdStLFDU,
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[]>, RegConstraint<"$addr.reg = $ea_result">;
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[]>, RegConstraint<"$addr.reg = $ea_result">,
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NoEncode<"$ea_result">;
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def LFDU : DForm_1<51, (ops F8RC:$rD, ptr_rc:$ea_result, memri:$addr),
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"lfd $rD, $addr", LdStLFD,
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[]>, RegConstraint<"$addr.reg = $ea_result">;
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[]>, RegConstraint<"$addr.reg = $ea_result">,
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NoEncode<"$ea_result">;
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}
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// Indexed (r+r) Loads.
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@ -499,13 +509,13 @@ def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src),
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// Unindexed (r+i) Stores.
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let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
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def STB : DForm_3<38, (ops GPRC:$rS, memri:$src),
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def STB : DForm_1<38, (ops GPRC:$rS, memri:$src),
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"stb $rS, $src", LdStGeneral,
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[(truncstorei8 GPRC:$rS, iaddr:$src)]>;
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def STH : DForm_3<44, (ops GPRC:$rS, memri:$src),
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def STH : DForm_1<44, (ops GPRC:$rS, memri:$src),
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"sth $rS, $src", LdStGeneral,
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[(truncstorei16 GPRC:$rS, iaddr:$src)]>;
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def STW : DForm_3<36, (ops GPRC:$rS, memri:$src),
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def STW : DForm_1<36, (ops GPRC:$rS, memri:$src),
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"stw $rS, $src", LdStGeneral,
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[(store GPRC:$rS, iaddr:$src)]>;
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def STFS : DForm_1<52, (ops F4RC:$rS, memri:$dst),
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@ -518,28 +528,33 @@ def STFD : DForm_1<54, (ops F8RC:$rS, memri:$dst),
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// Unindexed (r+i) Stores with Update (preinc).
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let isStore = 1, PPC970_Unit = 2 in {
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def STBU : DForm_3<39, (ops ptr_rc:$ea_res, GPRC:$rS, memri:$addr),
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def STBU : DForm_1<39, (ops ptr_rc:$ea_res, GPRC:$rS, memri:$addr),
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"stbu $rS, $addr", LdStGeneral,
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[/*(set ptr_rc:$ea_res,
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(pre_truncsti8 GPRC:$rS, iaddr:$addr))*/]>,
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RegConstraint<"$addr.reg = $ea_res">;
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def STHU : DForm_3<37, (ops ptr_rc:$ea_res, GPRC:$rS, memri:$addr),
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RegConstraint<"$addr.reg = $ea_res">,
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NoEncode<"$ea_res">;
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def STHU : DForm_1<37, (ops ptr_rc:$ea_res, GPRC:$rS, memri:$addr),
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"sthu $rS, $addr", LdStGeneral,
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[/*(set ptr_rc:$ea_res,
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(pre_truncsti16 GPRC:$rS, iaddr:$addr))*/]>,
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RegConstraint<"$addr.reg = $ea_res">;
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def STWU : DForm_3<37, (ops ptr_rc:$ea_res, GPRC:$rS, memri:$addr),
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RegConstraint<"$addr.reg = $ea_res">,
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NoEncode<"$ea_res">;
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def STWU : DForm_1<37, (ops ptr_rc:$ea_res, GPRC:$rS, memri:$addr),
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"stwu $rS, $addr", LdStGeneral,
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[/*(set ptr_rc:$ea_res, (pre_store GPRC:$rS, iaddr:$addr))*/]>,
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RegConstraint<"$addr.reg = $ea_res">;
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def STFSU : DForm_3<37, (ops ptr_rc:$ea_res, F4RC:$rS, memri:$addr),
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RegConstraint<"$addr.reg = $ea_res">,
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NoEncode<"$ea_res">;
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def STFSU : DForm_1<37, (ops ptr_rc:$ea_res, F4RC:$rS, memri:$addr),
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"stfsu $rS, $addr", LdStGeneral,
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[/*(set ptr_rc:$ea_res, (pre_store F4RC:$rS, iaddr:$addr))*/]>,
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RegConstraint<"$addr.reg = $ea_res">;
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def STFDU : DForm_3<37, (ops ptr_rc:$ea_res, F8RC:$rS, memri:$addr),
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RegConstraint<"$addr.reg = $ea_res">,
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NoEncode<"$ea_res">;
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def STFDU : DForm_1<37, (ops ptr_rc:$ea_res, F8RC:$rS, memri:$addr),
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"stfdu $rS, $addr", LdStGeneral,
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[/*(set ptr_rc:$ea_res, (pre_store F8RC:$rS, iaddr:$addr))*/]>,
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RegConstraint<"$addr.reg = $ea_res">;
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RegConstraint<"$addr.reg = $ea_res">,
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NoEncode<"$ea_res">;
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}
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@ -965,12 +980,13 @@ def FSUBS : AForm_2<59, 20,
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let PPC970_Unit = 1 in { // FXU Operations.
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// M-Form instructions. rotate and mask instructions.
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//
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let isTwoAddress = 1, isCommutable = 1 in {
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let isCommutable = 1 in {
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// RLWIMI can be commuted if the rotate amount is zero.
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def RLWIMI : MForm_2<20,
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(ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
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u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
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[]>, PPC970_DGroup_Cracked;
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[]>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
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NoEncode<"$rSi">;
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}
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def RLWINM : MForm_2<21,
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(ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
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