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R600: Add option to disable promote alloca

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This can make writing some tests harder, so add a flag
to disable it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212893 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-07-13 02:08:26 +00:00
parent 8ef1fa761f
commit 8e53751320
4 changed files with 24 additions and 5 deletions
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5
lib/Target/R600/AMDGPU.td
View File

@ -25,6 +25,11 @@ def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
"false", "false",
"Disable IR Structurizer">; "Disable IR Structurizer">;
def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
"EnablePromoteAlloca",
"true",
"Enable promote alloca pass">;
// Target features // Target features
def FeatureIfCvt : SubtargetFeature <"disable-ifcvt", def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",

9
lib/Target/R600/AMDGPUSubtarget.cpp
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@ -16,6 +16,8 @@
#include "R600InstrInfo.h" #include "R600InstrInfo.h"
#include "SIInstrInfo.h" #include "SIInstrInfo.h"
#include "llvm/ADT/SmallString.h"
using namespace llvm; using namespace llvm;
#define DEBUG_TYPE "amdgpu-subtarget" #define DEBUG_TYPE "amdgpu-subtarget"
@ -37,12 +39,17 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef GPU, StringRef FS) :
FP64(false), FP64(false),
CaymanISA(false), CaymanISA(false),
EnableIRStructurizer(true), EnableIRStructurizer(true),
EnablePromoteAlloca(false),
EnableIfCvt(true), EnableIfCvt(true),
WavefrontSize(0), WavefrontSize(0),
CFALUBug(false), CFALUBug(false),
LocalMemorySize(0), LocalMemorySize(0),
InstrItins(getInstrItineraryForCPU(GPU)) { InstrItins(getInstrItineraryForCPU(GPU)) {
ParseSubtargetFeatures(GPU, FS);
SmallString<256> FullFS("+promote-alloca,");
FullFS += FS;
ParseSubtargetFeatures(GPU, FullFS);
if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) { if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
InstrInfo.reset(new R600InstrInfo(*this)); InstrInfo.reset(new R600InstrInfo(*this));

7
lib/Target/R600/AMDGPUSubtarget.h
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@ -52,6 +52,7 @@ private:
bool FP64; bool FP64;
bool CaymanISA; bool CaymanISA;
bool EnableIRStructurizer; bool EnableIRStructurizer;
bool EnablePromoteAlloca;
bool EnableIfCvt; bool EnableIfCvt;
unsigned WavefrontSize; unsigned WavefrontSize;
bool CFALUBug; bool CFALUBug;
@ -81,7 +82,7 @@ public:
} }
short getTexVTXClauseSize() const { short getTexVTXClauseSize() const {
return TexVTXClauseSize; return TexVTXClauseSize;
} }
Generation getGeneration() const { Generation getGeneration() const {
@ -129,6 +130,10 @@ public:
return EnableIRStructurizer; return EnableIRStructurizer;
} }
bool isPromoteAllocaEnabled() const {
return EnablePromoteAlloca;
}
bool isIfCvtEnabled() const { bool isIfCvtEnabled() const {
return EnableIfCvt; return EnableIfCvt;
} }

8
lib/Target/R600/AMDGPUTargetMachine.cpp
View File

@ -33,7 +33,6 @@
#include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Scalar.h"
#include <llvm/CodeGen/Passes.h> #include <llvm/CodeGen/Passes.h>
using namespace llvm; using namespace llvm;
extern "C" void LLVMInitializeR600Target() { extern "C" void LLVMInitializeR600Target() {
@ -137,8 +136,11 @@ void AMDGPUTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
void AMDGPUPassConfig::addCodeGenPrepare() { void AMDGPUPassConfig::addCodeGenPrepare() {
const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>(); const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
addPass(createAMDGPUPromoteAlloca(ST)); if (ST.isPromoteAllocaEnabled()) {
addPass(createSROAPass()); addPass(createAMDGPUPromoteAlloca(ST));
addPass(createSROAPass());
}
TargetPassConfig::addCodeGenPrepare(); TargetPassConfig::addCodeGenPrepare();
} }