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https://github.com/c64scene-ar/llvm-6502.git
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Spill / restore should avoid modifying the condition register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33971 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
c67da0cf13
commit
8e59ea998f
@ -83,7 +83,7 @@ unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) co
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return MI->getOperand(0).getReg();
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}
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break;
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case ARM::tLDRspi:
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case ARM::tRestore:
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if (MI->getOperand(1).isFrameIndex() &&
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MI->getOperand(2).isImmediate() &&
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MI->getOperand(2).getImmedValue() == 0) {
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@ -117,7 +117,7 @@ unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) con
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return MI->getOperand(0).getReg();
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}
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break;
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case ARM::tSTRspi:
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case ARM::tSpill:
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if (MI->getOperand(1).isFrameIndex() &&
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MI->getOperand(2).isImmediate() &&
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MI->getOperand(2).getImmedValue() == 0) {
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@ -239,6 +239,11 @@ def tLDRspi : TIs<(ops GPR:$dst, t_addrmode_sp:$addr),
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"ldr $dst, $addr",
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[(set GPR:$dst, (load t_addrmode_sp:$addr))]>;
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// Special instruction for restore. It cannot clobber condition register
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// when it's expanded by eliminateCallFramePseudoInstr().
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def tRestore : TIs<(ops GPR:$dst, t_addrmode_sp:$addr),
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"ldr $dst, $addr", []>;
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// Load tconstpool
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def tLDRpci : TIs<(ops GPR:$dst, i32imm:$addr),
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"ldr $dst, $addr",
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@ -261,6 +266,11 @@ def tSTRH : TI2<(ops GPR:$src, t_addrmode_s2:$addr),
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def tSTRspi : TIs<(ops GPR:$src, t_addrmode_sp:$addr),
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"str $src, $addr",
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[(store GPR:$src, t_addrmode_sp:$addr)]>;
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// Special instruction for spill. It cannot clobber condition register
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// when it's expanded by eliminateCallFramePseudoInstr().
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def tSpill : TIs<(ops GPR:$src, t_addrmode_sp:$addr),
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"str $src, $addr", []>;
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}
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//===----------------------------------------------------------------------===//
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@ -130,7 +130,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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MachineFunction &MF = *MBB.getParent();
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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if (AFI->isThumbFunction())
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BuildMI(MBB, I, TII.get(ARM::tSTRspi)).addReg(SrcReg)
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BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg)
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.addFrameIndex(FI).addImm(0);
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else
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BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg)
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@ -153,7 +153,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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MachineFunction &MF = *MBB.getParent();
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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if (AFI->isThumbFunction())
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BuildMI(MBB, I, TII.get(ARM::tLDRspi), DestReg)
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BuildMI(MBB, I, TII.get(ARM::tRestore), DestReg)
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.addFrameIndex(FI).addImm(0);
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else
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BuildMI(MBB, I, TII.get(ARM::LDR), DestReg)
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@ -220,16 +220,16 @@ MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI,
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if (OpNum == 0) { // move -> store
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unsigned SrcReg = MI->getOperand(1).getReg();
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if (!isLowRegister(SrcReg))
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// tSTRspi cannot take a high register operand.
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// tSpill cannot take a high register operand.
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break;
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NewMI = BuildMI(TII.get(ARM::tSTRspi)).addReg(SrcReg).addFrameIndex(FI)
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NewMI = BuildMI(TII.get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI)
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.addImm(0);
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} else { // move -> load
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unsigned DstReg = MI->getOperand(0).getReg();
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if (!isLowRegister(DstReg))
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// tLDRspi cannot target a high register operand.
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// tRestore cannot target a high register operand.
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break;
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NewMI = BuildMI(TII.get(ARM::tLDRspi), DstReg).addFrameIndex(FI)
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NewMI = BuildMI(TII.get(ARM::tRestore), DstReg).addFrameIndex(FI)
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.addImm(0);
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}
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break;
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@ -412,7 +412,7 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
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if (isSub) Bytes = -NumBytes;
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bool isMul4 = (Bytes & 3) == 0;
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bool isTwoAddr = false;
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bool DstNeBase = false;
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bool DstNotEqBase = false;
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unsigned NumBits = 1;
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unsigned Scale = 1;
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int Opc = 0;
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@ -441,14 +441,14 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
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// r1 = sub sp, c
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// r8 = sub sp, c
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if (DestReg != BaseReg)
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DstNeBase = true;
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DstNotEqBase = true;
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NumBits = 8;
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Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
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isTwoAddr = true;
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}
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unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
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unsigned Threshold = (DestReg == ARM::SP) ? 4 : 3;
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unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
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if (NumMIs > Threshold) {
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// This will expand into too many instructions. Load the immediate from a
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// constpool entry.
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@ -456,7 +456,7 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
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return;
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}
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if (DstNeBase) {
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if (DstNotEqBase) {
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if (isLowRegister(DestReg) && isLowRegister(BaseReg)) {
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// If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
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unsigned Chunk = (1 << 3) - 1;
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@ -730,27 +730,20 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
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isSub = true;
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}
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if (!isSub || !isThumb) {
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MachineOperand &ImmOp = MI.getOperand(ImmIdx);
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int ImmedOffset = Offset / Scale;
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unsigned Mask = (1 << NumBits) - 1;
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if ((unsigned)Offset <= Mask * Scale) {
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// Replace the FrameIndex with sp
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MI.getOperand(i).ChangeToRegister(FrameReg, false);
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if (isSub)
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ImmedOffset |= 1 << NumBits;
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ImmOp.ChangeToImmediate(ImmedOffset);
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return;
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}
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MachineOperand &ImmOp = MI.getOperand(ImmIdx);
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int ImmedOffset = Offset / Scale;
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unsigned Mask = (1 << NumBits) - 1;
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if ((unsigned)Offset <= Mask * Scale) {
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// Replace the FrameIndex with sp
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MI.getOperand(i).ChangeToRegister(FrameReg, false);
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if (isSub)
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ImmedOffset |= 1 << NumBits;
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ImmOp.ChangeToImmediate(ImmedOffset);
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return;
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}
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if (!isThumb) {
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// Otherwise, it didn't fit. Pull in what we can to simplify the immed.
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if (AddrMode == ARMII::AddrModeTs) {
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// Thumb tLDRspi, tSTRspi. These will change to instructions that use
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// a different base register.
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NumBits = 5;
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Mask = (1 << NumBits) - 1;
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}
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ImmedOffset = ImmedOffset & Mask;
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if (isSub)
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ImmedOffset |= 1 << NumBits;
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@ -768,8 +761,12 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
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if (TII.isLoad(Opcode)) {
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// Use the destination register to materialize sp + offset.
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unsigned TmpReg = MI.getOperand(0).getReg();
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emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg,
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isSub ? -Offset : Offset, TII);
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if (Opcode == ARM::tRestore)
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emitThumbRegPlusConstPool(MBB, II, TmpReg, FrameReg,
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isSub ? -Offset : Offset, TII);
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else
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emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg,
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isSub ? -Offset : Offset, TII);
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MI.setInstrDescriptor(TII.get(ARM::tLDR));
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MI.getOperand(i).ChangeToRegister(TmpReg, false);
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MI.addRegOperand(0, false); // tLDR has an extra register operand.
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@ -788,8 +785,12 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
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BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R2);
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TmpReg = ARM::R2;
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}
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emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg,
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isSub ? -Offset : Offset, TII);
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if (Opcode == ARM::tSpill)
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emitThumbRegPlusConstPool(MBB, II, TmpReg, FrameReg,
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isSub ? -Offset : Offset, TII);
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else
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emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg,
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isSub ? -Offset : Offset, TII);
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MI.setInstrDescriptor(TII.get(ARM::tSTR));
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MI.getOperand(i).ChangeToRegister(TmpReg, false);
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MI.addRegOperand(0, false); // tSTR has an extra register operand.
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@ -1098,7 +1099,7 @@ static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
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static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
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return ((MI->getOpcode() == ARM::FLDD ||
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MI->getOpcode() == ARM::LDR ||
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MI->getOpcode() == ARM::tLDRspi) &&
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MI->getOpcode() == ARM::tRestore) &&
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MI->getOperand(1).isFrameIndex() &&
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isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
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}
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@ -124,3 +124,20 @@ L12:
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.align 2
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L11:
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.long 642
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//===---------------------------------------------------------------------===//
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When spilling in thumb mode and the sp offset is too large to fit in the ldr /
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str offset field, we load the offset from a constpool entry and add it to sp:
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ldr r2, LCPI
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add r2, sp
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ldr r2, [r2]
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These instructions preserve the condition code which is important if the spill
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is between a cmp and a bcc instruction. However, we can use the (potentially)
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cheaper sequnce if we know it's ok to clobber the condition register.
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add r2, sp, #255 * 4
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add r2, #132
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ldr r2, [r2, #7 * 4]
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