From 8e5c0da84892649254def8782dc041539209d4db Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Thu, 9 Apr 2009 02:33:36 +0000 Subject: [PATCH] Don't copy the operand of a SwitchInst into virtual registers as eagerly. This helps avoid CopyToReg nodes in some cases where they aren't needed, and also helps subsequent optimizer heuristics in cases where the extra nodes would cause the node to appear to have multiple results. This doesn't have a significant impact currently; it'll help an upcoming change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68667 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp index ba59906b6da..fd15603d990 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp @@ -243,9 +243,7 @@ static bool isUsedOutsideOfDefiningBlock(Instruction *I) { if (isa(I)) return true; BasicBlock *BB = I->getParent(); for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI) - if (cast(*UI)->getParent() != BB || isa(*UI) || - // FIXME: Remove switchinst special case. - isa(*UI)) + if (cast(*UI)->getParent() != BB || isa(*UI)) return true; return false; } @@ -1640,6 +1638,9 @@ bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, if (I != E-1) { FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); CurMF->insert(BBI, FallThrough); + + // Put SV in a virtual register to make it available from the new blocks. + ExportFromCurrentBlock(SV); } else { // If the last case doesn't match, go to the default block. FallThrough = Default; @@ -1874,6 +1875,9 @@ bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); CurMF->insert(BBI, TrueBB); WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); + + // Put SV in a virtual register to make it available from the new blocks. + ExportFromCurrentBlock(SV); } // Similar to the optimization above, if the Value being switched on is @@ -1888,6 +1892,9 @@ bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); CurMF->insert(BBI, FalseBB); WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); + + // Put SV in a virtual register to make it available from the new blocks. + ExportFromCurrentBlock(SV); } // Create a CaseBlock record representing a conditional branch to @@ -2013,6 +2020,9 @@ bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, BTC.push_back(BitTestCase(CasesBits[i].Mask, CaseBB, CasesBits[i].BB)); + + // Put SV in a virtual register to make it available from the new blocks. + ExportFromCurrentBlock(SV); } BitTestBlock BTB(lowBound, cmpRange, SV,