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Two changes, both very significant:

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* vreg <-> vreg joining now works, enable it unconditionally when joining
  is enabled (which is the default).
* Fix a serious pessimization of spill code where we were saying that a
  spilled DEF operand was live into the subsequent instruction.  This allows
  for substantially better code when spilling starts to happen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14993 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-07-19 05:55:50 +00:00
parent 57eb15e316
commit 8ea13c6233
1 changed files with 2 additions and 11 deletions
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13
lib/CodeGen/LiveIntervalAnalysis.cpp
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@ -60,11 +60,6 @@ namespace {
EnableJoining("join-liveintervals", EnableJoining("join-liveintervals",
cl::desc("Join compatible live intervals"), cl::desc("Join compatible live intervals"),
cl::init(true)); cl::init(true));
cl::opt<bool>
EnableVirtVirtJoining("join-liveintervals-virtvirtjoining",
cl::desc("Join live intervals for virtreg pairs (buggy)"),
cl::init(false));
}; };
void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const
@ -251,7 +246,7 @@ std::vector<LiveInterval*> LiveIntervals::addIntervalsForSpills(
// use of the next instruction. Otherwise we end // use of the next instruction. Otherwise we end
// after the use of this instruction. // after the use of this instruction.
unsigned end = 1 + (mop.isDef() ? unsigned end = 1 + (mop.isDef() ?
getUseIndex(index+InstrSlots::NUM) : getStoreIndex(index) :
getUseIndex(index)); getUseIndex(index));
// create a new register for this spill // create a new register for this spill
@ -545,11 +540,7 @@ void LiveIntervals::joinIntervals()
Intervals::iterator intB = r2iB->second; Intervals::iterator intB = r2iB->second;
// both A and B are virtual registers // both A and B are virtual registers
if (MRegisterInfo::isVirtualRegister(intA->reg) &&
// FIXME: coallescing two virtual registers together is
// apparently broken.
if (EnableVirtVirtJoining &&
MRegisterInfo::isVirtualRegister(intA->reg) &&
MRegisterInfo::isVirtualRegister(intB->reg)) { MRegisterInfo::isVirtualRegister(intB->reg)) {
const TargetRegisterClass *rcA, *rcB; const TargetRegisterClass *rcA, *rcB;