mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-06 04:31:08 +00:00
MachineInstr now inherits from Annotable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2647 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
1e2ddcf741
commit
8eb04905e8
@ -10,6 +10,7 @@
|
|||||||
#define LLVM_CODEGEN_MACHINEINSTR_H
|
#define LLVM_CODEGEN_MACHINEINSTR_H
|
||||||
|
|
||||||
#include "llvm/Target/MachineInstrInfo.h"
|
#include "llvm/Target/MachineInstrInfo.h"
|
||||||
|
#include "llvm/Annotation.h"
|
||||||
#include <iterator>
|
#include <iterator>
|
||||||
class Instruction;
|
class Instruction;
|
||||||
|
|
||||||
@ -232,7 +233,8 @@ MachineOperand::InitializeReg(int _regNum, bool isCCReg)
|
|||||||
// a CALL (if any), and return value of a RETURN.
|
// a CALL (if any), and return value of a RETURN.
|
||||||
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
class MachineInstr : public NonCopyable {
|
class MachineInstr : public Annotable, // Values are annotable
|
||||||
|
public NonCopyableV { // Disable copy operations
|
||||||
MachineOpCode opCode;
|
MachineOpCode opCode;
|
||||||
OpCodeMask opCodeMask; // extra bits for variants of an opcode
|
OpCodeMask opCodeMask; // extra bits for variants of an opcode
|
||||||
std::vector<MachineOperand> operands;
|
std::vector<MachineOperand> operands;
|
||||||
|
Loading…
Reference in New Issue
Block a user