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Prevent ARM assembler from losing a right shift by #32 applied to a register

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159937 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Barton
2012-07-09 16:31:14 +00:00
parent c985e6ece6
commit 8ed97ef5f6
2 changed files with 36 additions and 1 deletions
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4
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@@ -7247,7 +7247,9 @@ processInstruction(MCInst &Inst,
case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
}
// If the shift is by zero, use the non-shifted instruction definition.
if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0) {
// The exception is for right shifts, where 0 == 32
if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
!(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
MCInst TmpInst;
TmpInst.setOpcode(newOpc);
TmpInst.addOperand(Inst.getOperand(0));