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https://github.com/c64scene-ar/llvm-6502.git
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Improve 256-bit shuffle splitting to allow 2 sources in each 128-bit lane. As long as only a single lane of the source is used in the lane in the destination. This makes the splitting match much closer to what happens with 256-bit shuffles when AVX is disabled and only 128-bit XMM is allowed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148537 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
38b6d9dd22
commit
8f35c13842
@ -3162,17 +3162,6 @@ static bool isUndefOrInRange(int Val, int Low, int Hi) {
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return (Val < 0) || (Val >= Low && Val < Hi);
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}
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/// isUndefOrInRange - Return true if every element in Mask, begining
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/// from position Pos and ending in Pos+Size, falls within the specified
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/// range (L, L+Pos]. or is undef.
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static bool isUndefOrInRange(ArrayRef<int> Mask,
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int Pos, int Size, int Low, int Hi) {
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for (int i = Pos, e = Pos+Size; i != e; ++i)
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if (!isUndefOrInRange(Mask[i], Low, Hi))
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return false;
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return true;
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}
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/// isUndefOrEqual - Val is either less than zero (undef) or equal to the
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/// specified value.
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static bool isUndefOrEqual(int Val, int CmpVal) {
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@ -5948,95 +5937,106 @@ static SDValue getVZextMovL(EVT VT, EVT OpVT,
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OpVT, SrcOp)));
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}
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/// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector
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/// shuffle node referes to only one lane in the sources.
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static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) {
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EVT VT = SVOp->getValueType(0);
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int NumElems = VT.getVectorNumElements();
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int HalfSize = NumElems/2;
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ArrayRef<int> M = SVOp->getMask();
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bool MatchA = false, MatchB = false;
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for (int l = 0; l < NumElems*2; l += HalfSize) {
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if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) {
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MatchA = true;
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break;
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}
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}
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for (int l = 0; l < NumElems*2; l += HalfSize) {
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if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) {
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MatchB = true;
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break;
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}
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}
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return MatchA && MatchB;
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}
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/// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
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/// which could not be matched by any known target speficic shuffle
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static SDValue
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LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
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if (areShuffleHalvesWithinDisjointLanes(SVOp)) {
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// If each half of a vector shuffle node referes to only one lane in the
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// source vectors, extract each used 128-bit lane and shuffle them using
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// 128-bit shuffles. Then, concatenate the results. Otherwise leave
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// the work to the legalizer.
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DebugLoc dl = SVOp->getDebugLoc();
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EVT VT = SVOp->getValueType(0);
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int NumElems = VT.getVectorNumElements();
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int HalfSize = NumElems/2;
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EVT VT = SVOp->getValueType(0);
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// Extract the reference for each half
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int FstVecExtractIdx = 0, SndVecExtractIdx = 0;
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int FstVecOpNum = 0, SndVecOpNum = 0;
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for (int i = 0; i < HalfSize; ++i) {
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int Elt = SVOp->getMaskElt(i);
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if (SVOp->getMaskElt(i) < 0)
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unsigned NumElems = VT.getVectorNumElements();
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unsigned NumLaneElems = NumElems / 2;
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int MinRange[2][2] = { { static_cast<int>(NumElems),
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static_cast<int>(NumElems) },
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{ static_cast<int>(NumElems),
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static_cast<int>(NumElems) } };
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int MaxRange[2][2] = { { -1, -1 }, { -1, -1 } };
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// Collect used ranges for each source in each lane
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for (unsigned l = 0; l < 2; ++l) {
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unsigned LaneStart = l*NumLaneElems;
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for (unsigned i = 0; i != NumLaneElems; ++i) {
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int Idx = SVOp->getMaskElt(i+LaneStart);
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if (Idx < 0)
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continue;
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FstVecOpNum = Elt/NumElems;
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FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
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break;
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}
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for (int i = HalfSize; i < NumElems; ++i) {
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int Elt = SVOp->getMaskElt(i);
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if (SVOp->getMaskElt(i) < 0)
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continue;
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SndVecOpNum = Elt/NumElems;
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SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
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break;
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}
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// Extract the subvectors
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SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum),
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DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl);
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SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum),
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DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl);
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int Input = 0;
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if (Idx >= (int)NumElems) {
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Idx -= NumElems;
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Input = 1;
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}
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// Generate 128-bit shuffles
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SmallVector<int, 16> MaskV1, MaskV2;
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for (int i = 0; i < HalfSize; ++i) {
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int Elt = SVOp->getMaskElt(i);
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MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize);
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if (Idx > MaxRange[l][Input])
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MaxRange[l][Input] = Idx;
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if (Idx < MinRange[l][Input])
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MinRange[l][Input] = Idx;
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}
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for (int i = HalfSize; i < NumElems; ++i) {
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int Elt = SVOp->getMaskElt(i);
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MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize);
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}
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EVT NVT = V1.getValueType();
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V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]);
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V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]);
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// Concatenate the result back
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SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1,
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DAG.getConstant(0, MVT::i32), DAG, dl);
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return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
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DAG, dl);
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}
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return SDValue();
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// Make sure each range is 128-bits
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int ExtractIdx[2][2] = { { -1, -1 }, { -1, -1 } };
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for (unsigned l = 0; l < 2; ++l) {
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for (unsigned Input = 0; Input < 2; ++Input) {
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if (MinRange[l][Input] == (int)NumElems && MaxRange[l][Input] < 0)
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continue;
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if (MinRange[l][Input] >= 0 && MinRange[l][Input] < (int)NumLaneElems)
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ExtractIdx[l][Input] = 0;
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else if (MinRange[l][Input] >= (int)NumLaneElems &&
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MinRange[l][Input] < (int)NumElems)
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ExtractIdx[l][Input] = NumLaneElems;
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else
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return SDValue();
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}
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}
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DebugLoc dl = SVOp->getDebugLoc();
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MVT EltVT = VT.getVectorElementType().getSimpleVT();
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EVT NVT = MVT::getVectorVT(EltVT, NumElems/2);
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SDValue Ops[2][2];
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for (unsigned l = 0; l < 2; ++l) {
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for (unsigned Input = 0; Input < 2; ++Input) {
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if (ExtractIdx[l][Input] >= 0)
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Ops[l][Input] = Extract128BitVector(SVOp->getOperand(Input),
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DAG.getConstant(ExtractIdx[l][Input], MVT::i32),
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DAG, dl);
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else
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Ops[l][Input] = DAG.getUNDEF(NVT);
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}
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}
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// Generate 128-bit shuffles
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SmallVector<int, 16> Mask1, Mask2;
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for (unsigned i = 0; i != NumLaneElems; ++i) {
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int Elt = SVOp->getMaskElt(i);
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if (Elt >= (int)NumElems) {
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Elt %= NumLaneElems;
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Elt += NumLaneElems;
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} else if (Elt >= 0) {
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Elt %= NumLaneElems;
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}
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Mask1.push_back(Elt);
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}
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for (unsigned i = NumLaneElems; i != NumElems; ++i) {
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int Elt = SVOp->getMaskElt(i);
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if (Elt >= (int)NumElems) {
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Elt %= NumLaneElems;
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Elt += NumLaneElems;
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} else if (Elt >= 0) {
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Elt %= NumLaneElems;
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}
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Mask2.push_back(Elt);
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}
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SDValue Shuf1 = DAG.getVectorShuffle(NVT, dl, Ops[0][0], Ops[0][1], &Mask1[0]);
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SDValue Shuf2 = DAG.getVectorShuffle(NVT, dl, Ops[1][0], Ops[1][1], &Mask2[0]);
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// Concatenate the result back
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SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Shuf1,
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DAG.getConstant(0, MVT::i32), DAG, dl);
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return Insert128BitVector(V, Shuf2, DAG.getConstant(NumElems/2, MVT::i32),
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DAG, dl);
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}
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/// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
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