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https://github.com/c64scene-ar/llvm-6502.git
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Move class and instruction definitions for conditional moves to a seperate file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142220 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
eea367ec97
commit
8f3af87e99
107
lib/Target/Mips/MipsCondMov.td
Normal file
107
lib/Target/Mips/MipsCondMov.td
Normal file
@ -0,0 +1,107 @@
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// Conditional moves:
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// These instructions are expanded in
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// MipsISelLowering::EmitInstrWithCustomInserter if target does not have
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// conditional move instructions.
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// cond:int, data:int
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class CondMovIntInt<bits<6> funct, string instr_asm> :
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FR<0, funct, (outs CPURegs:$rd), (ins CPURegs:$rs, CPURegs:$rt, CPURegs:$F),
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!strconcat(instr_asm, "\t$rd, $rs, $rt"), [], NoItinerary> {
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let shamt = 0;
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let usesCustomInserter = 1;
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let Constraints = "$F = $rd";
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}
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// cond:int, data:float
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class CondMovIntFP<RegisterClass RC, bits<5> fmt, bits<6> func,
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string instr_asm> :
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FFR<0x11, func, fmt, (outs RC:$fd), (ins RC:$fs, CPURegs:$rt, RC:$F),
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!strconcat(instr_asm, "\t$fd, $fs, $rt"), []> {
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let usesCustomInserter = 1;
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let Constraints = "$F = $fd";
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}
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// cond:float, data:int
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class CondMovFPInt<SDNode cmov, bits<1> tf, string instr_asm> :
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FCMOV<tf, (outs CPURegs:$rd), (ins CPURegs:$rs, CPURegs:$F),
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!strconcat(instr_asm, "\t$rd, $rs, $$fcc0"),
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[(set CPURegs:$rd, (cmov CPURegs:$rs, CPURegs:$F))]> {
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let cc = 0;
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let usesCustomInserter = 1;
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let Uses = [FCR31];
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let Constraints = "$F = $rd";
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}
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// cond:float, data:float
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class CondMovFPFP<RegisterClass RC, SDNode cmov, bits<5> fmt, bits<1> tf,
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string instr_asm> :
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FFCMOV<fmt, tf, (outs RC:$fd), (ins RC:$fs, RC:$F),
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!strconcat(instr_asm, "\t$fd, $fs, $$fcc0"),
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[(set RC:$fd, (cmov RC:$fs, RC:$F))]> {
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let cc = 0;
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let usesCustomInserter = 1;
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let Uses = [FCR31];
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let Constraints = "$F = $fd";
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}
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// select patterns
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multiclass MovzPats<RegisterClass RC, Instruction MOVZInst> {
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def : Pat<(select (i32 (setge CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
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(MOVZInst RC:$T, (SLT CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
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def : Pat<(select (i32 (setuge CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
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(MOVZInst RC:$T, (SLTu CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
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def : Pat<(select (i32 (setge CPURegs:$lhs, immSExt16:$rhs)), RC:$T, RC:$F),
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(MOVZInst RC:$T, (SLTi CPURegs:$lhs, immSExt16:$rhs), RC:$F)>;
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def : Pat<(select (i32 (setuge CPURegs:$lh, immSExt16:$rh)), RC:$T, RC:$F),
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(MOVZInst RC:$T, (SLTiu CPURegs:$lh, immSExt16:$rh), RC:$F)>;
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def : Pat<(select (i32 (setle CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
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(MOVZInst RC:$T, (SLT CPURegs:$rhs, CPURegs:$lhs), RC:$F)>;
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def : Pat<(select (i32 (setule CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
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(MOVZInst RC:$T, (SLTu CPURegs:$rhs, CPURegs:$lhs), RC:$F)>;
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def : Pat<(select (i32 (seteq CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
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(MOVZInst RC:$T, (XOR CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
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def : Pat<(select (i32 (seteq CPURegs:$lhs, 0)), RC:$T, RC:$F),
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(MOVZInst RC:$T, CPURegs:$lhs, RC:$F)>;
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}
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multiclass MovnPats<RegisterClass RC, Instruction MOVNInst> {
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def : Pat<(select (i32 (setne CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
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(MOVNInst RC:$T, (XOR CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
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def : Pat<(select CPURegs:$cond, RC:$T, RC:$F),
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(MOVNInst RC:$T, CPURegs:$cond, RC:$F)>;
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def : Pat<(select (i32 (setne CPURegs:$lhs, 0)), RC:$T, RC:$F),
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(MOVNInst RC:$T, CPURegs:$lhs, RC:$F)>;
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}
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// Instantiation of instructions.
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def MOVZ_I : CondMovIntInt<0x0a, "movz">;
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def MOVN_I : CondMovIntInt<0x0b, "movn">;
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def MOVZ_S : CondMovIntFP<FGR32, 16, 18, "movz.s">;
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def MOVN_S : CondMovIntFP<FGR32, 16, 19, "movn.s">;
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let Predicates = [NotFP64bit] in {
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def MOVZ_D : CondMovIntFP<AFGR64, 17, 18, "movz.d">;
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def MOVN_D : CondMovIntFP<AFGR64, 17, 19, "movn.d">;
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}
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def MOVT : CondMovFPInt<MipsCMovFP_T, 1, "movt">;
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def MOVF : CondMovFPInt<MipsCMovFP_F, 0, "movf">;
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def MOVT_S : CondMovFPFP<FGR32, MipsCMovFP_T, 16, 1, "movt.s">;
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def MOVF_S : CondMovFPFP<FGR32, MipsCMovFP_F, 16, 0, "movf.s">;
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let Predicates = [NotFP64bit] in {
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def MOVT_D : CondMovFPFP<AFGR64, MipsCMovFP_T, 17, 1, "movt.d">;
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def MOVF_D : CondMovFPFP<AFGR64, MipsCMovFP_F, 17, 0, "movf.d">;
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}
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// Instantiation of conditional move patterns.
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defm : MovzPats<CPURegs, MOVZ_I>;
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defm : MovnPats<CPURegs, MOVN_I>;
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defm : MovzPats<FGR32, MOVZ_S>;
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defm : MovnPats<FGR32, MOVN_S>;
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let Predicates = [NotFP64bit] in {
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defm : MovzPats<AFGR64, MOVZ_D>;
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defm : MovnPats<AFGR64, MOVN_D>;
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}
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@ -259,59 +259,6 @@ let Defs=[FCR31] in {
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Requires<[NotFP64bit]>;
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}
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// Conditional moves:
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// These instructions are expanded in
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// MipsISelLowering::EmitInstrWithCustomInserter if target does not have
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// conditional move instructions.
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// flag:int, data:float
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let usesCustomInserter = 1, Constraints = "$F = $dst" in
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class CondMovIntFP<RegisterClass RC, bits<5> fmt, bits<6> func,
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string instr_asm> :
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FFR<0x11, func, fmt, (outs RC:$dst), (ins RC:$T, CPURegs:$cond, RC:$F),
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!strconcat(instr_asm, "\t$dst, $T, $cond"), []>;
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def MOVZ_S : CondMovIntFP<FGR32, 16, 18, "movz.s">;
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def MOVN_S : CondMovIntFP<FGR32, 16, 19, "movn.s">;
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let Predicates = [NotFP64bit] in {
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def MOVZ_D : CondMovIntFP<AFGR64, 17, 18, "movz.d">;
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def MOVN_D : CondMovIntFP<AFGR64, 17, 19, "movn.d">;
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}
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defm : MovzPats<FGR32, MOVZ_S>;
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defm : MovnPats<FGR32, MOVN_S>;
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let Predicates = [NotFP64bit] in {
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defm : MovzPats<AFGR64, MOVZ_D>;
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defm : MovnPats<AFGR64, MOVN_D>;
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}
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let usesCustomInserter = 1, Uses = [FCR31], Constraints = "$F = $dst" in {
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// flag:float, data:int
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class CondMovFPInt<SDNode cmov, bits<1> tf, string instr_asm> :
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FCMOV<tf, (outs CPURegs:$dst), (ins CPURegs:$T, CPURegs:$F),
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!strconcat(instr_asm, "\t$dst, $T, $$fcc0"),
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[(set CPURegs:$dst, (cmov CPURegs:$T, CPURegs:$F))]>;
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// flag:float, data:float
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class CondMovFPFP<RegisterClass RC, SDNode cmov, bits<5> fmt, bits<1> tf,
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string instr_asm> :
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FFCMOV<fmt, tf, (outs RC:$dst), (ins RC:$T, RC:$F),
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!strconcat(instr_asm, "\t$dst, $T, $$fcc0"),
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[(set RC:$dst, (cmov RC:$T, RC:$F))]>;
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}
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def MOVT : CondMovFPInt<MipsCMovFP_T, 1, "movt">;
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def MOVF : CondMovFPInt<MipsCMovFP_F, 0, "movf">;
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def MOVT_S : CondMovFPFP<FGR32, MipsCMovFP_T, 16, 1, "movt.s">;
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def MOVF_S : CondMovFPFP<FGR32, MipsCMovFP_F, 16, 0, "movf.s">;
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let Predicates = [NotFP64bit] in {
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def MOVT_D : CondMovFPFP<AFGR64, MipsCMovFP_T, 17, 1, "movt.d">;
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def MOVF_D : CondMovFPFP<AFGR64, MipsCMovFP_F, 17, 0, "movf.d">;
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}
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//===----------------------------------------------------------------------===//
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// Floating Point Pseudo-Instructions
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//===----------------------------------------------------------------------===//
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@ -205,14 +205,14 @@ class FCMOV<bits<1> _tf, dag outs, dag ins, string asmstr,
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{
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bits<5> rd;
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bits<5> rs;
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bits<3> N;
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bits<3> cc;
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bits<1> tf;
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let opcode = 0;
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let tf = _tf;
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let Inst{25-21} = rs;
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let Inst{20-18} = N;
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let Inst{20-18} = cc;
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let Inst{17} = 0;
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let Inst{16} = tf;
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let Inst{15-11} = rd;
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@ -226,7 +226,7 @@ class FFCMOV<bits<5> _fmt, bits<1> _tf, dag outs, dag ins, string asmstr,
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{
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bits<5> fd;
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bits<5> fs;
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bits<3> N;
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bits<3> cc;
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bits<5> fmt;
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bits<1> tf;
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@ -235,7 +235,7 @@ class FFCMOV<bits<5> _fmt, bits<1> _tf, dag outs, dag ins, string asmstr,
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let tf = _tf;
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let Inst{25-21} = fmt;
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let Inst{20-18} = N;
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let Inst{20-18} = cc;
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let Inst{17} = 0;
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let Inst{16} = tf;
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let Inst{15-11} = fs;
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@ -769,23 +769,6 @@ def CLO : CountLeading1<0x21, "clo", CPURegs>;
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/// Byte Swap
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def WSBW : ByteSwap<0x20, 0x2, "wsbw">;
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// Conditional moves:
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// These instructions are expanded in
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// MipsISelLowering::EmitInstrWithCustomInserter if target does not have
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// conditional move instructions.
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// flag:int, data:int
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class CondMovIntInt<bits<6> funct, string instr_asm> :
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FR<0, funct, (outs CPURegs:$rd),
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(ins CPURegs:$rs, CPURegs:$rt, CPURegs:$F),
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!strconcat(instr_asm, "\t$rd, $rs, $rt"), [], NoItinerary> {
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let shamt = 0;
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let usesCustomInserter = 1;
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let Constraints = "$F = $rd";
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}
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def MOVZ_I : CondMovIntInt<0x0a, "movz">;
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def MOVN_I : CondMovIntInt<0x0b, "movn">;
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/// No operation
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let addr=0 in
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def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
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@ -948,38 +931,6 @@ def : Pat<(brcond RC:$cond, bb:$dst),
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defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
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// select patterns
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multiclass MovzPats<RegisterClass RC, Instruction MOVZInst> {
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def : Pat<(select (i32 (setge CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
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(MOVZInst RC:$T, (SLT CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
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def : Pat<(select (i32 (setuge CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
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(MOVZInst RC:$T, (SLTu CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
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def : Pat<(select (i32 (setge CPURegs:$lhs, immSExt16:$rhs)), RC:$T, RC:$F),
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(MOVZInst RC:$T, (SLTi CPURegs:$lhs, immSExt16:$rhs), RC:$F)>;
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def : Pat<(select (i32 (setuge CPURegs:$lh, immSExt16:$rh)), RC:$T, RC:$F),
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(MOVZInst RC:$T, (SLTiu CPURegs:$lh, immSExt16:$rh), RC:$F)>;
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def : Pat<(select (i32 (setle CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
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(MOVZInst RC:$T, (SLT CPURegs:$rhs, CPURegs:$lhs), RC:$F)>;
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def : Pat<(select (i32 (setule CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
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(MOVZInst RC:$T, (SLTu CPURegs:$rhs, CPURegs:$lhs), RC:$F)>;
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def : Pat<(select (i32 (seteq CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
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(MOVZInst RC:$T, (XOR CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
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def : Pat<(select (i32 (seteq CPURegs:$lhs, 0)), RC:$T, RC:$F),
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(MOVZInst RC:$T, CPURegs:$lhs, RC:$F)>;
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}
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multiclass MovnPats<RegisterClass RC, Instruction MOVNInst> {
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def : Pat<(select (i32 (setne CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
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(MOVNInst RC:$T, (XOR CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
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def : Pat<(select CPURegs:$cond, RC:$T, RC:$F),
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(MOVNInst RC:$T, CPURegs:$cond, RC:$F)>;
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def : Pat<(select (i32 (setne CPURegs:$lhs, 0)), RC:$T, RC:$F),
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(MOVNInst RC:$T, CPURegs:$lhs, RC:$F)>;
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}
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defm : MovzPats<CPURegs, MOVZ_I>;
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defm : MovnPats<CPURegs, MOVN_I>;
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// setcc patterns
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multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
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Instruction SLTuOp, Register ZEROReg> {
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@ -1032,5 +983,6 @@ def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
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//===----------------------------------------------------------------------===//
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include "MipsInstrFPU.td"
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include "MipsCondMov.td"
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include "Mips64InstrInfo.td"
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