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Minor compile-time optimization; don't bother checking

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canClobberPhysRegDefs if the successor node doesn't
clobber any physical registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67587 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2009-03-24 00:50:07 +00:00
parent 002b44f1d7
commit 8f4aa333d0
1 changed files with 1 additions and 1 deletions
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2
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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@ -1392,7 +1392,7 @@ void RegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
continue; continue;
// Don't constrain nodes with physical register defs if the // Don't constrain nodes with physical register defs if the
// predecessor can clobber them. // predecessor can clobber them.
if (SuccSU->hasPhysRegDefs) { if (SuccSU->hasPhysRegDefs && SU->hasPhysRegClobbers) {
if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI)) if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI))
continue; continue;
} }