rename hasVariableOperands() -> isVariadic(). Add some comments.

Evan, please review the comments I added to getNumDefs to make sure
that they are accurate, thx.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45687 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/Target/TargetInstrInfo.h

@@ -125,9 +125,7 @@ const unsigned M_TERMINATOR_FLAG       = 1 << 11;
 // block.
 const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 12;
 
-// M_VARIABLE_OPS - Set if this instruction can have a variable number of extra
+const unsigned M_VARIADIC          = 1 << 13;
-// operands in addition to the minimum number operands specified.
-const unsigned M_VARIABLE_OPS          = 1 << 13;
 
 // M_PREDICABLE - Set if this instruction has a predicate operand that
 // controls execution. It may be set to 'always'.
@@ -141,8 +139,6 @@ const unsigned M_REMATERIALIZIBLE      = 1 << 15;
 // (e.g. instructions with unique labels attached).
 const unsigned M_NOT_DUPLICABLE        = 1 << 16;
 
-// M_HAS_OPTIONAL_DEF - Set if this instruction has an optional definition, e.g.
-// ARM instructions which can set condition code if 's' bit is set.
 const unsigned M_HAS_OPTIONAL_DEF      = 1 << 17;
 
 // M_NEVER_HAS_SIDE_EFFECTS - Set if this instruction has no side effects that
@@ -182,7 +178,7 @@ public:
   /// it is set. Returns -1 if it is not set.
   int getOperandConstraint(unsigned OpNum,
                            TOI::OperandConstraint Constraint) const {
-    assert((OpNum < NumOperands || hasVariableOperands()) &&
+    assert((OpNum < NumOperands || isVariadic()) &&
            "Invalid operand # of TargetInstrInfo");
     if (OpNum < NumOperands &&
         (OpInfo[OpNum].Constraints & (1 << Constraint))) {
@@ -202,18 +198,32 @@ public:
     return Name;
   }
   
+  /// getNumOperands - Return the number of declared MachineOperands for this
+  /// MachineInstruction.  Note that variadic (isVariadic() returns true)
+  /// instructions may have additional operands at the end of the list, and note
+  /// that the machine instruction may include implicit register def/uses as
+  /// well.
   unsigned getNumOperands() const {
     return NumOperands;
   }
   
+  /// getNumDefs - Return the number of MachineOperands that are register
+  /// definitions.  Register definitions always occur at the start of the 
+  /// machine operand list.  This is the number of "outs" in the .td file.
   unsigned getNumDefs() const {
     return NumDefs;
   }
   
-  bool hasVariableOperands() const {
+  /// isVariadic - Return true if this instruction can have a variable number of
-    return Flags & M_VARIABLE_OPS;
+  /// operands.  In this case, the variable operands will be after the normal
+  /// operands but before the implicit definitions and uses (if any are
+  /// present).
+  bool isVariadic() const {
+    return Flags & M_VARIADIC;
   }
   
+  /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
+  /// ARM instructions which can set condition code if 's' bit is set.
   bool hasOptionalDef() const {
     return Flags & M_HAS_OPTIONAL_DEF;
   }

lib/CodeGen/MachineInstr.cpp

@@ -488,8 +488,7 @@ MachineInstr *MachineInstr::removeFromParent() {
 ///
 bool MachineInstr::OperandsComplete() const {
   unsigned short NumOperands = TID->getNumOperands();
-  if (TID->hasVariableOperands() == 0 &&
+  if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
-      getNumOperands()-NumImplicitOps >= NumOperands)
     return true;  // Broken: we have all the operands of this instruction!
   return false;
 }
@@ -498,7 +497,7 @@ bool MachineInstr::OperandsComplete() const {
 ///
 unsigned MachineInstr::getNumExplicitOperands() const {
   unsigned NumOperands = TID->getNumOperands();
-  if (TID->hasVariableOperands() == 0)
+  if (!TID->isVariadic())
     return NumOperands;
 
   for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {

lib/CodeGen/SelectionDAG/ScheduleDAG.cpp

@@ -294,7 +294,7 @@ static const TargetRegisterClass *getInstrOperandRegClass(
         const TargetInstrDescriptor *II,
         unsigned Op) {
   if (Op >= II->getNumOperands()) {
-    assert((II->Flags & M_VARIABLE_OPS)&& "Invalid operand # of instruction");
+    assert(II->isVariadic() && "Invalid operand # of instruction");
     return NULL;
   }
   if (II->OpInfo[Op].isLookupPtrRegClass())
@@ -678,7 +678,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
                           II.getImplicitDefs() != 0;
 #ifndef NDEBUG
     assert((II.getNumOperands() == NumMIOperands ||
-            HasPhysRegOuts || II.hasVariableOperands()) &&
+            HasPhysRegOuts || II.isVariadic()) &&
            "#operands for dag node doesn't match .td file!"); 
 #endif
 

lib/Target/X86/X86CodeEmitter.cpp

@@ -799,6 +799,5 @@ void Emitter::emitInstruction(const MachineInstr &MI,
     break;
   }
 
-  assert((Desc->Flags & M_VARIABLE_OPS) != 0 ||
+  assert((Desc->isVariadic() || CurOp == NumOps) && "Unknown encoding!");
-         CurOp == NumOps && "Unknown encoding!");
 }

utils/TableGen/CodeGenInstruction.cpp

@@ -99,7 +99,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
   mayHaveSideEffects = R->getValueAsBit("mayHaveSideEffects");
   neverHasSideEffects = R->getValueAsBit("neverHasSideEffects");
   hasOptionalDef = false;
-  hasVariableNumberOfOperands = false;
+  isVariadic = false;
 
   if (mayHaveSideEffects && neverHasSideEffects)
     throw R->getName() +
@@ -159,7 +159,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
       else if (Rec->isSubClassOf("OptionalDefOperand"))
         hasOptionalDef = true;
     } else if (Rec->getName() == "variable_ops") {
-      hasVariableNumberOfOperands = true;
+      isVariadic = true;
       continue;
     } else if (!Rec->isSubClassOf("RegisterClass") && 
                Rec->getName() != "ptr_rc")

utils/TableGen/CodeGenInstruction.h

@@ -99,7 +99,7 @@ namespace llvm {
     bool isReMaterializable;
     bool hasDelaySlot;
     bool usesCustomDAGSchedInserter;
-    bool hasVariableNumberOfOperands;
+    bool isVariadic;
     bool hasCtrlDep;
     bool isNotDuplicable;
     bool hasOptionalDef;

utils/TableGen/DAGISelEmitter.cpp

@@ -835,7 +835,7 @@ public:
       if (InstPatNode && InstPatNode->getOperator()->getName() == "set") {
         InstPatNode = InstPatNode->getChild(InstPatNode->getNumChildren()-1);
       }
-      bool HasVarOps     = isRoot && II.hasVariableNumberOfOperands;
+      bool HasVarOps     = isRoot && II.isVariadic;
       // FIXME: fix how we deal with physical register operands.
       bool HasImpInputs  = isRoot && Inst.getNumImpOperands() > 0;
       bool HasImpResults = isRoot && DstRegs.size() > 0;

utils/TableGen/InstrInfoEmitter.cpp

@@ -320,9 +320,9 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
   if (Inst.hasOptionalDef)     OS << "|M_HAS_OPTIONAL_DEF";
   if (Inst.usesCustomDAGSchedInserter)
     OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
-  if (Inst.hasVariableNumberOfOperands) OS << "|M_VARIABLE_OPS";
+  if (Inst.isVariadic)         OS << "|M_VARIADIC";
-  if (Inst.mayHaveSideEffects)          OS << "|M_MAY_HAVE_SIDE_EFFECTS";
+  if (Inst.mayHaveSideEffects) OS << "|M_MAY_HAVE_SIDE_EFFECTS";
-  if (NeverHasSideEffects)              OS << "|M_NEVER_HAS_SIDE_EFFECTS";
+  if (NeverHasSideEffects)     OS << "|M_NEVER_HAS_SIDE_EFFECTS";
   OS << ", 0";
 
   // Emit all of the target-specific flags...