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define the Addr1BinOp class

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30979 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola
2006-10-16 18:18:14 +00:00
parent 15a6c3e976
commit 90057aaeb7
1 changed files with 14 additions and 34 deletions
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48
lib/Target/ARM/ARMInstrInfo.td
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@@ -51,6 +51,11 @@ class IntBinOp<string OpcStr, SDNode OpNode> :
!strconcat(OpcStr, " $dst, $a, $b"), !strconcat(OpcStr, " $dst, $a, $b"),
[(set IntRegs:$dst, (OpNode IntRegs:$a, IntRegs:$b))]>; [(set IntRegs:$dst, (OpNode IntRegs:$a, IntRegs:$b))]>;
class Addr1BinOp<string OpcStr, SDNode OpNode> :
InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
!strconcat(OpcStr, " $dst, $a, $b"),
[(set IntRegs:$dst, (OpNode IntRegs:$a, addr_mode1:$b))]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instructions // Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@@ -144,17 +149,9 @@ def str : InstARM<(ops IntRegs:$src, memri:$addr),
def MOV : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src), def MOV : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
"mov $dst, $src", [(set IntRegs:$dst, addr_mode1:$src)]>; "mov $dst, $src", [(set IntRegs:$dst, addr_mode1:$src)]>;
def ADD : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b), def ADD : Addr1BinOp<"add", add>;
"add $dst, $a, $b", def ADCS : Addr1BinOp<"adcs", adde>;
[(set IntRegs:$dst, (add IntRegs:$a, addr_mode1:$b))]>; def ADDS : Addr1BinOp<"adds", addc>;
def ADCS : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
"adcs $dst, $a, $b",
[(set IntRegs:$dst, (adde IntRegs:$a, addr_mode1:$b))]>;
def ADDS : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
"adds $dst, $a, $b",
[(set IntRegs:$dst, (addc IntRegs:$a, addr_mode1:$b))]>;
// "LEA" forms of add // "LEA" forms of add
def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr), def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
@@ -162,29 +159,12 @@ def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
[(set IntRegs:$dst, iaddr:$addr)]>; [(set IntRegs:$dst, iaddr:$addr)]>;
def SUB : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b), def SUB : Addr1BinOp<"sub", sub>;
"sub $dst, $a, $b", def SBCS : Addr1BinOp<"sbcs", sube>;
[(set IntRegs:$dst, (sub IntRegs:$a, addr_mode1:$b))]>; def SUBS : Addr1BinOp<"subs", subc>;
def AND : Addr1BinOp<"and", and>;
def SBCS : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b), def EOR : Addr1BinOp<"eor", xor>;
"sbcs $dst, $a, $b", def ORR : Addr1BinOp<"orr", or>;
[(set IntRegs:$dst, (sube IntRegs:$a, addr_mode1:$b))]>;
def SUBS : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
"subs $dst, $a, $b",
[(set IntRegs:$dst, (subc IntRegs:$a, addr_mode1:$b))]>;
def AND : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
"and $dst, $a, $b",
[(set IntRegs:$dst, (and IntRegs:$a, addr_mode1:$b))]>;
def EOR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
"eor $dst, $a, $b",
[(set IntRegs:$dst, (xor IntRegs:$a, addr_mode1:$b))]>;
def ORR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
"orr $dst, $a, $b",
[(set IntRegs:$dst, (or IntRegs:$a, addr_mode1:$b))]>;
let isTwoAddress = 1 in { let isTwoAddress = 1 in {
def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false, def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false,