6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-26 21:32:10 +00:00
Code Issues Projects Releases Wiki Activity

For AArch64 Neon, simplify scalar dup by lane0 for fp.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198194 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jiangning Liu 2013-12-30 02:44:35 +00:00
parent afcdbf7400
commit 90128bee68
2 changed files with 39 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
lib/Target/AArch64/AArch64InstrNEON.td
View File

@ -5954,23 +5954,28 @@ def DUPdv_D : NeonI_Scalar_DUP<"dup", "d", FPR64, VPR128, neon_uimm1_bare> {
let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0}; let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
} }
multiclass NeonI_Scalar_DUP_Elt_pattern<Instruction DUPI, ValueType ResTy, def : Pat<(f32 (vector_extract (v4f32 VPR128:$Rn), 0)),
ValueType OpTy, Operand OpImm, (f32 (EXTRACT_SUBREG (v4f32 VPR128:$Rn), sub_32))>;
ValueType OpNTy, ValueType ExTy, Operand OpNImm> { def : Pat<(f32 (vector_extract (v4f32 VPR128:$Rn), 1)),
def : Pat<(ResTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)), (f32 (DUPsv_S (v4f32 VPR128:$Rn), 1))>;
(ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>; def : Pat<(f32 (vector_extract (v4f32 VPR128:$Rn), 2)),
(f32 (DUPsv_S (v4f32 VPR128:$Rn), 2))>;
def : Pat<(f32 (vector_extract (v4f32 VPR128:$Rn), 3)),
(f32 (DUPsv_S (v4f32 VPR128:$Rn), 3))>;
def : Pat<(ResTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)), def : Pat<(f64 (vector_extract (v2f64 VPR128:$Rn), 0)),
(ResTy (DUPI (f64 (EXTRACT_SUBREG (v2f64 VPR128:$Rn), sub_64))>;
(ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)), def : Pat<(f64 (vector_extract (v2f64 VPR128:$Rn), 1)),
OpNImm:$Imm))>; (f64 (DUPdv_D (v2f64 VPR128:$Rn), 1))>;
}
// Patterns for vector extract of FP data using scalar DUP instructions def : Pat<(f32 (vector_extract (v2f32 VPR64:$Rn), 0)),
defm : NeonI_Scalar_DUP_Elt_pattern<DUPsv_S, f32, (f32 (EXTRACT_SUBREG (v2f32 VPR64:$Rn), sub_32))>;
v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>; def : Pat<(f32 (vector_extract (v2f32 VPR64:$Rn), 1)),
defm : NeonI_Scalar_DUP_Elt_pattern<DUPdv_D, f64, (f32 (DUPsv_S (v4f32 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>; 1))>;
def : Pat<(f64 (vector_extract (v1f64 VPR64:$Rn), 0)),
(f64 (EXTRACT_SUBREG (v1f64 VPR64:$Rn), sub_64))>;
multiclass NeonI_Scalar_DUP_Ext_Vec_pattern<Instruction DUPI, multiclass NeonI_Scalar_DUP_Ext_Vec_pattern<Instruction DUPI,
ValueType ResTy, ValueType OpTy,Operand OpLImm, ValueType ResTy, ValueType OpTy,Operand OpLImm,

21
test/CodeGen/AArch64/neon-scalar-copy.ll
View File

@ -7,9 +7,18 @@ define float @test_dup_sv2S(<2 x float> %v) {
ret float %tmp1 ret float %tmp1
} }
define float @test_dup_sv2S_0(<2 x float> %v) {
;CHECK-LABEL: test_dup_sv2S_0
;CHECK-NOT: dup {{s[0-9]+}}, {{v[0-9]+}}.s[0]
;CHECK: ret
%tmp1 = extractelement <2 x float> %v, i32 0
ret float %tmp1
}
define float @test_dup_sv4S(<4 x float> %v) { define float @test_dup_sv4S(<4 x float> %v) {
;CHECK: test_dup_sv4S ;CHECK-LABEL: test_dup_sv4S
;CHECK: dup {{s[0-9]+}}, {{v[0-9]+}}.s[0] ;CHECK-NOT: dup {{s[0-9]+}}, {{v[0-9]+}}.s[0]
;CHECK: ret
%tmp1 = extractelement <4 x float> %v, i32 0 %tmp1 = extractelement <4 x float> %v, i32 0
ret float %tmp1 ret float %tmp1
} }
@ -29,6 +38,14 @@ define double @test_dup_dv2D(<2 x double> %v) {
ret double %tmp1 ret double %tmp1
} }
define double @test_dup_dv2D_0(<2 x double> %v) {
;CHECK: test_dup_dv2D_0
;CHECK-NOT: dup {{d[0-9]+}}, {{v[0-9]+}}.d[0]
;CHECK: ret
%tmp1 = extractelement <2 x double> %v, i32 1
ret double %tmp1
}
define <1 x i8> @test_vector_dup_bv16B(<16 x i8> %v1) { define <1 x i8> @test_vector_dup_bv16B(<16 x i8> %v1) {
;CHECK: test_vector_dup_bv16B ;CHECK: test_vector_dup_bv16B
;CHECK: dup {{b[0-9]+}}, {{v[0-9]+}}.b[14] ;CHECK: dup {{b[0-9]+}}, {{v[0-9]+}}.b[14]