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Fold some patterns into instruction definitons so tablegen can infer flags removing the need for an explicit 'neverHasSideEffects = 1'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162656 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -383,7 +383,8 @@ let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
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// load of an all-zeros value if folding it would be beneficial.
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let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
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isPseudo = 1, neverHasSideEffects = 1 in {
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def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "", []>;
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def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
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[(set VR128:$dst, (v4f32 immAllZerosV))]>;
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}
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def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
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@ -409,13 +410,12 @@ def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
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def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
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[(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
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}
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let Predicates = [HasAVX2], neverHasSideEffects = 1 in
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let Predicates = [HasAVX2] in
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def AVX2_SET0 : PDI<0xef, MRMInitReg, (outs VR256:$dst), (ins), "",
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[]>, VEX_4V;
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[(set VR256:$dst, (v4i64 immAllZerosV))]>, VEX_4V;
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}
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let Predicates = [HasAVX2] in {
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def : Pat<(v4i64 immAllZerosV), (AVX2_SET0)>;
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def : Pat<(v8i32 immAllZerosV), (AVX2_SET0)>;
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def : Pat<(v16i16 immAllZerosV), (AVX2_SET0)>;
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def : Pat<(v32i8 immAllZerosV), (AVX2_SET0)>;
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