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Add ROTR and ROTRV mips32 instructions. Patch by Akira Hatanaka

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121377 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2010-12-09 17:32:30 +00:00
parent 90c595425b
commit 908b6ddad6
3 changed files with 68 additions and 13 deletions
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5
lib/Target/Mips/MipsISelLowering.cpp
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@ -115,7 +115,10 @@ MipsTargetLowering(MipsTargetMachine &TM)
setOperationAction(ISD::CTPOP, MVT::i32, Expand);
setOperationAction(ISD::CTTZ, MVT::i32, Expand);
setOperationAction(ISD::ROTL, MVT::i32, Expand);
setOperationAction(ISD::ROTR, MVT::i32, Expand);
if (!Subtarget->isMips32r2())
setOperationAction(ISD::ROTR, MVT::i32, Expand);
setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);

36
lib/Target/Mips/MipsInstrInfo.td
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@ -60,6 +60,7 @@ def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
def HasSwap : Predicate<"Subtarget.hasSwap()">;
def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
def IsMips32 : Predicate<"Subtarget.isMips32()">;
def IsMips32r2 : Predicate<"Subtarget.isMips32r2()">;
//===----------------------------------------------------------------------===//
// Mips Operand, Complex Patterns and Transformations Definitions.
@ -168,16 +169,21 @@ class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
[(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
// Shifts
let rt = 0 in
class LogicR_shift_imm<bits<6> func, string instr_asm, SDNode OpNode>:
class LogicR_shift_rotate_imm<bits<6> func, bits<5> _rs, string instr_asm,
SDNode OpNode>:
FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, shamt:$c),
!strconcat(instr_asm, "\t$dst, $b, $c"),
[(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu>;
[(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu> {
let rs = _rs;
}
class LogicR_shift_reg<bits<6> func, string instr_asm, SDNode OpNode>:
FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
class LogicR_shift_rotate_reg<bits<6> func, bits<5> _shamt, string instr_asm,
SDNode OpNode>:
FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$c, CPURegs:$b),
!strconcat(instr_asm, "\t$dst, $b, $c"),
[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu> {
let shamt = _shamt;
}
// Load Upper Imediate
class LoadUpper<bits<6> op, string instr_asm>:
@ -376,12 +382,18 @@ def XOR : LogicR<0x26, "xor", xor>;
def NOR : LogicNOR<0x00, 0x27, "nor">;
/// Shift Instructions
def SLL : LogicR_shift_imm<0x00, "sll", shl>;
def SRL : LogicR_shift_imm<0x02, "srl", srl>;
def SRA : LogicR_shift_imm<0x03, "sra", sra>;
def SLLV : LogicR_shift_reg<0x04, "sllv", shl>;
def SRLV : LogicR_shift_reg<0x06, "srlv", srl>;
def SRAV : LogicR_shift_reg<0x07, "srav", sra>;
def SLL : LogicR_shift_rotate_imm<0x00, 0x00, "sll", shl>;
def SRL : LogicR_shift_rotate_imm<0x02, 0x00, "srl", srl>;
def SRA : LogicR_shift_rotate_imm<0x03, 0x00, "sra", sra>;
def SLLV : LogicR_shift_rotate_reg<0x04, 0x00, "sllv", shl>;
def SRLV : LogicR_shift_rotate_reg<0x06, 0x00, "srlv", srl>;
def SRAV : LogicR_shift_rotate_reg<0x07, 0x00, "srav", sra>;
// Rotate Instructions
let Predicates = [IsMips32r2] in {
def ROTR : LogicR_shift_rotate_imm<0x02, 0x01, "rotr", rotr>;
def ROTRV : LogicR_shift_rotate_reg<0x06, 0x01, "rotrv", rotr>;
}
/// Load and Store Instructions
def LB : LoadM<0x20, "lb", sextloadi8>;

40
test/CodeGen/Mips/rotate.ll Normal file
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@ -0,0 +1,40 @@
; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
; CHECK: rotrv $2, $4, $2
define i32 @rot0(i32 %a, i32 %b) nounwind readnone {
entry:
%shl = shl i32 %a, %b
%sub = sub i32 32, %b
%shr = lshr i32 %a, %sub
%or = or i32 %shr, %shl
ret i32 %or
}
; CHECK: rotr $2, $4, 22
define i32 @rot1(i32 %a) nounwind readnone {
entry:
%shl = shl i32 %a, 10
%shr = lshr i32 %a, 22
%or = or i32 %shl, %shr
ret i32 %or
}
; CHECK: rotrv $2, $4, $5
define i32 @rot2(i32 %a, i32 %b) nounwind readnone {
entry:
%shr = lshr i32 %a, %b
%sub = sub i32 32, %b
%shl = shl i32 %a, %sub
%or = or i32 %shl, %shr
ret i32 %or
}
; CHECK: rotr $2, $4, 10
define i32 @rot3(i32 %a) nounwind readnone {
entry:
%shr = lshr i32 %a, 10
%shl = shl i32 %a, 22
%or = or i32 %shr, %shl
ret i32 %or
}