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Don't enforce ordered inline asm operands.

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I was too optimistic, inline asm can have tied operands that don't
follow the def order.

Fixes PR13742.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162998 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2012-08-31 15:34:59 +00:00
parent cb5f63d7fa
commit 908c0c01f6
2 changed files with 9 additions and 10 deletions
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10
lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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@@ -895,7 +895,6 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
// Remember to operand index of the group flags. // Remember to operand index of the group flags.
SmallVector<unsigned, 8> GroupIdx; SmallVector<unsigned, 8> GroupIdx;
unsigned PrevDefGroup = 0;
// Add all of the operand registers to the instruction. // Add all of the operand registers to the instruction.
for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
@@ -944,15 +943,6 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) { if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
unsigned DefGroup = 0; unsigned DefGroup = 0;
if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) { if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
// Check that the def groups are monotonically increasing.
// Otherwise, the tied uses and defs won't line up, and
// MI::findTiedOperandIdx() will find the wrong operand. This
// should be automatically enforced by the front ends when
// translating "+" constraints into tied def+use pairs.
assert(DefGroup >= PrevDefGroup &&
"Tied inline asm operands must be in increasing order.");
PrevDefGroup = DefGroup;
unsigned DefIdx = GroupIdx[DefGroup] + 1; unsigned DefIdx = GroupIdx[DefGroup] + 1;
unsigned UseIdx = GroupIdx.back() + 1; unsigned UseIdx = GroupIdx.back() + 1;
for (unsigned j = 0; j != NumVals; ++j) { for (unsigned j = 0; j != NumVals; ++j) {

9
test/CodeGen/X86/inline-asm-tied.ll
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@@ -19,3 +19,12 @@ entry:
%1 = load i64* %retval ; <i64> [#uses=1] %1 = load i64* %retval ; <i64> [#uses=1]
ret i64 %1 ret i64 %1
} }
; The tied operands are not necessarily in the same order as the defs.
; PR13742
define i64 @swapped(i64 %x, i64 %y) nounwind {
entry:
%x0 = call { i64, i64 } asm "foo", "=r,=r,1,0,~{dirflag},~{fpsr},~{flags}"(i64 %x, i64 %y) nounwind
%x1 = extractvalue { i64, i64 } %x0, 0
ret i64 %x1
}