6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-09 13:33:17 +00:00
Code Issues Projects Releases Wiki Activity

ARM NEON: Don't need COPY_TO_REGCLASS in pattern

Browse Source 
In my previous commit:
"Merge a f32 bitcast of a v2i32 extractelt

A vectorized sitfp on doubles will get scalarized to a sequence of an
extract_element of <2 x i32>, a bitcast to f32 and a sitofp.
Due to the the extract_element, and the bitcast we will uneccessarily generate
moves between scalar and vector registers."

I added a pattern containing a copy_to_regclass. The copy_to_regclass is
actually not needed.

radar://13191881

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175555 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Arnold Schwaighofer 2013-02-19 20:16:45 +00:00
parent 03544ec2a4
commit 909a0e0e95
1 changed files with 1 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/ARM/ARMInstrNEON.td
View File

@ -5747,9 +5747,7 @@ def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
// Fold extracting an element out of a v2i32 into a vfp register.
def : Pat<(f32 (bitconvert (i32 (extractelt (v2i32 DPR:$src), imm:$lane)))),
(f32 (EXTRACT_SUBREG
(v2f32 (COPY_TO_REGCLASS (v2i32 DPR:$src), DPR)),
(SSubReg_f32_reg imm:$lane)))>;
(f32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
// Vector lengthening move with load, matching extending loads.