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No functionality change:

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- Constified some MachineOperand values.
 - Added/Modified some comments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47358 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
2008-02-20 06:10:21 +00:00
parent 359026e39a
commit 90a3868fe5
1 changed files with 42 additions and 31 deletions
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73
lib/CodeGen/LiveVariables.cpp
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@@ -59,6 +59,7 @@ void LiveVariables::VarInfo::dump() const {
} }
} }
/// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) { LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
assert(TargetRegisterInfo::isVirtualRegister(RegIdx) && assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
"getVarInfo: not a virtual register!"); "getVarInfo: not a virtual register!");
@@ -75,37 +76,45 @@ LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
return VI; return VI;
} }
/// KillsRegister - Returns true if the machine instruction kills the specified
/// register.
bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const { bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i); const MachineOperand &MO = MI->getOperand(i);
if (MO.isRegister() && MO.isKill()) { if (MO.isRegister() && MO.isKill()) {
if ((MO.getReg() == Reg) || unsigned MOReg = MO.getReg();
(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && if (MOReg == Reg ||
(TargetRegisterInfo::isPhysicalRegister(MOReg) &&
TargetRegisterInfo::isPhysicalRegister(Reg) && TargetRegisterInfo::isPhysicalRegister(Reg) &&
RegInfo->isSubRegister(MO.getReg(), Reg))) RegInfo->isSubRegister(MOReg, Reg)))
return true; return true;
} }
} }
return false; return false;
} }
/// RegisterDefIsDead - Returns true if the register is dead in this machine
/// instruction.
bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const { bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i); const MachineOperand &MO = MI->getOperand(i);
if (MO.isRegister() && MO.isDead()) { if (MO.isRegister() && MO.isDead()) {
if ((MO.getReg() == Reg) || unsigned MOReg = MO.getReg();
(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && if ((MOReg == Reg) ||
(TargetRegisterInfo::isPhysicalRegister(MOReg) &&
TargetRegisterInfo::isPhysicalRegister(Reg) && TargetRegisterInfo::isPhysicalRegister(Reg) &&
RegInfo->isSubRegister(MO.getReg(), Reg))) RegInfo->isSubRegister(MOReg, Reg)))
return true; return true;
} }
} }
return false; return false;
} }
/// ModifiesRegister - Returns true if the machine instruction modifies the
/// register.
bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const { bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i); const MachineOperand &MO = MI->getOperand(i);
if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg) if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
return true; return true;
} }
@@ -119,7 +128,7 @@ void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
unsigned BBNum = MBB->getNumber(); unsigned BBNum = MBB->getNumber();
// Check to see if this basic block is one of the killing blocks. If so, // Check to see if this basic block is one of the killing blocks. If so,
// remove it... // remove it.
for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i) for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
if (VRInfo.Kills[i]->getParent() == MBB) { if (VRInfo.Kills[i]->getParent() == MBB) {
VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
@@ -163,9 +172,9 @@ void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
VRInfo.UsedBlocks[BBNum] = true; VRInfo.UsedBlocks[BBNum] = true;
VRInfo.NumUses++; VRInfo.NumUses++;
// Check to see if this basic block is already a kill block... // Check to see if this basic block is already a kill block.
if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) { if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
// Yes, this register is killed in this basic block already. Increase the // Yes, this register is killed in this basic block already. Increase the
// live range by updating the kill instruction. // live range by updating the kill instruction.
VRInfo.Kills.back() = MI; VRInfo.Kills.back() = MI;
return; return;
@@ -179,10 +188,9 @@ void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
assert(MBB != MRI.getVRegDef(reg)->getParent() && assert(MBB != MRI.getVRegDef(reg)->getParent() &&
"Should have kill for defblock!"); "Should have kill for defblock!");
// Add a new kill entry for this basic block. // Add a new kill entry for this basic block. If this virtual register is
// If this virtual register is already marked as alive in this basic block, // already marked as alive in this basic block, that means it is alive in at
// that means it is alive in at least one of the successor block, it's not // least one of the successor blocks, it's not a kill.
// a kill.
if (!VRInfo.AliveBlocks[BBNum]) if (!VRInfo.AliveBlocks[BBNum])
VRInfo.Kills.push_back(MI); VRInfo.Kills.push_back(MI);
@@ -202,6 +210,7 @@ void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
true/*IsImp*/,true/*IsKill*/)); true/*IsImp*/,true/*IsKill*/));
Def->addOperand(MachineOperand::CreateReg(Reg,true/*IsDef*/,true/*IsImp*/)); Def->addOperand(MachineOperand::CreateReg(Reg,true/*IsDef*/,true/*IsImp*/));
} }
PhysRegPartDef[Reg].clear(); PhysRegPartDef[Reg].clear();
// There was an earlier def of a super-register. Add implicit def to that MI. // There was an earlier def of a super-register. Add implicit def to that MI.
@@ -419,29 +428,31 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
// Process all uses... // Process all uses...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) { for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i); const MachineOperand &MO = MI->getOperand(i);
if (MO.isRegister() && MO.isUse() && MO.getReg()) { if (MO.isRegister() && MO.isUse() && MO.getReg()) {
if (TargetRegisterInfo::isVirtualRegister(MO.getReg())){ unsigned MOReg = MO.getReg();
HandleVirtRegUse(MO.getReg(), MBB, MI); if (TargetRegisterInfo::isVirtualRegister(MOReg))
} else if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && HandleVirtRegUse(MOReg, MBB, MI);
!ReservedRegisters[MO.getReg()]) { else if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
HandlePhysRegUse(MO.getReg(), MI); !ReservedRegisters[MOReg])
} HandlePhysRegUse(MOReg, MI);
} }
} }
// Process all defs... // Process all defs...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) { for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i); const MachineOperand &MO = MI->getOperand(i);
if (MO.isRegister() && MO.isDef() && MO.getReg()) { if (MO.isRegister() && MO.isDef() && MO.getReg()) {
if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned MOReg = MO.getReg();
VarInfo &VRInfo = getVarInfo(MO.getReg()); if (TargetRegisterInfo::isVirtualRegister(MOReg)) {
VarInfo &VRInfo = getVarInfo(MOReg);
if (VRInfo.AliveBlocks.none()) if (VRInfo.AliveBlocks.none())
// If vr is not alive in any block, then defaults to dead. // If vr is not alive in any block, then defaults to dead.
VRInfo.Kills.push_back(MI); VRInfo.Kills.push_back(MI);
} else if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && } else if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
!ReservedRegisters[MO.getReg()]) { !ReservedRegisters[MOReg]) {
HandlePhysRegDef(MO.getReg(), MI); HandlePhysRegDef(MOReg, MI);
} }
} }
} }
@@ -599,6 +610,6 @@ void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end(); for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
PHIVarInfo[BBI->getOperand(i + 1).getMBB()->getNumber()]. PHIVarInfo[BBI->getOperand(i + 1).getMBB()->getNumber()]
push_back(BBI->getOperand(i).getReg()); .push_back(BBI->getOperand(i).getReg());
} }