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mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-25 16:31:33 +00:00

rearrange some code, no functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48101 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2008-03-09 07:58:04 +00:00
parent d9c4c450bf
commit 90b347dc90

@ -1404,35 +1404,7 @@ void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC, const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const { const TargetRegisterClass *SrcRC) const {
if (DestRC != SrcRC) { if (DestRC == SrcRC) {
// Moving EFLAGS to / from another register requires a push and a pop.
if (SrcRC == &X86::CCRRegClass) {
assert(SrcReg == X86::EFLAGS);
if (DestRC == &X86::GR64RegClass) {
BuildMI(MBB, MI, get(X86::PUSHFQ));
BuildMI(MBB, MI, get(X86::POP64r), DestReg);
return;
} else if (DestRC == &X86::GR32RegClass) {
BuildMI(MBB, MI, get(X86::PUSHFD));
BuildMI(MBB, MI, get(X86::POP32r), DestReg);
return;
}
} else if (DestRC == &X86::CCRRegClass) {
assert(DestReg == X86::EFLAGS);
if (SrcRC == &X86::GR64RegClass) {
BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg);
BuildMI(MBB, MI, get(X86::POPFQ));
return;
} else if (SrcRC == &X86::GR32RegClass) {
BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg);
BuildMI(MBB, MI, get(X86::POPFD));
return;
}
}
cerr << "Not yet supported!";
abort();
}
unsigned Opc; unsigned Opc;
if (DestRC == &X86::GR64RegClass) { if (DestRC == &X86::GR64RegClass) {
Opc = X86::MOV64rr; Opc = X86::MOV64rr;
@ -1465,6 +1437,35 @@ void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
abort(); abort();
} }
BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg); BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg);
return;
}
// Moving EFLAGS to / from another register requires a push and a pop.
if (SrcRC == &X86::CCRRegClass) {
assert(SrcReg == X86::EFLAGS);
if (DestRC == &X86::GR64RegClass) {
BuildMI(MBB, MI, get(X86::PUSHFQ));
BuildMI(MBB, MI, get(X86::POP64r), DestReg);
return;
} else if (DestRC == &X86::GR32RegClass) {
BuildMI(MBB, MI, get(X86::PUSHFD));
BuildMI(MBB, MI, get(X86::POP32r), DestReg);
return;
}
} else if (DestRC == &X86::CCRRegClass) {
assert(DestReg == X86::EFLAGS);
if (SrcRC == &X86::GR64RegClass) {
BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg);
BuildMI(MBB, MI, get(X86::POPFQ));
return;
} else if (SrcRC == &X86::GR32RegClass) {
BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg);
BuildMI(MBB, MI, get(X86::POPFD));
return;
}
}
cerr << "Not yet supported!";
abort();
} }
static unsigned getStoreRegOpcode(const TargetRegisterClass *RC, static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,