mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-25 16:31:33 +00:00
rearrange some code, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48101 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1404,35 +1404,7 @@ void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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unsigned DestReg, unsigned SrcReg,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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const TargetRegisterClass *SrcRC) const {
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if (DestRC != SrcRC) {
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if (DestRC == SrcRC) {
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// Moving EFLAGS to / from another register requires a push and a pop.
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if (SrcRC == &X86::CCRRegClass) {
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assert(SrcReg == X86::EFLAGS);
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if (DestRC == &X86::GR64RegClass) {
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BuildMI(MBB, MI, get(X86::PUSHFQ));
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BuildMI(MBB, MI, get(X86::POP64r), DestReg);
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return;
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} else if (DestRC == &X86::GR32RegClass) {
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BuildMI(MBB, MI, get(X86::PUSHFD));
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BuildMI(MBB, MI, get(X86::POP32r), DestReg);
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return;
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}
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} else if (DestRC == &X86::CCRRegClass) {
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assert(DestReg == X86::EFLAGS);
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if (SrcRC == &X86::GR64RegClass) {
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BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg);
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BuildMI(MBB, MI, get(X86::POPFQ));
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return;
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} else if (SrcRC == &X86::GR32RegClass) {
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BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg);
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BuildMI(MBB, MI, get(X86::POPFD));
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return;
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}
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}
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cerr << "Not yet supported!";
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abort();
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}
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unsigned Opc;
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unsigned Opc;
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if (DestRC == &X86::GR64RegClass) {
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if (DestRC == &X86::GR64RegClass) {
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Opc = X86::MOV64rr;
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Opc = X86::MOV64rr;
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@ -1465,6 +1437,35 @@ void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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abort();
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abort();
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}
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}
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BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg);
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BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg);
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return;
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}
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// Moving EFLAGS to / from another register requires a push and a pop.
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if (SrcRC == &X86::CCRRegClass) {
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assert(SrcReg == X86::EFLAGS);
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if (DestRC == &X86::GR64RegClass) {
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BuildMI(MBB, MI, get(X86::PUSHFQ));
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BuildMI(MBB, MI, get(X86::POP64r), DestReg);
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return;
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} else if (DestRC == &X86::GR32RegClass) {
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BuildMI(MBB, MI, get(X86::PUSHFD));
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BuildMI(MBB, MI, get(X86::POP32r), DestReg);
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return;
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}
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} else if (DestRC == &X86::CCRRegClass) {
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assert(DestReg == X86::EFLAGS);
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if (SrcRC == &X86::GR64RegClass) {
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BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg);
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BuildMI(MBB, MI, get(X86::POPFQ));
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return;
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} else if (SrcRC == &X86::GR32RegClass) {
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BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg);
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BuildMI(MBB, MI, get(X86::POPFD));
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return;
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}
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}
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cerr << "Not yet supported!";
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abort();
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}
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}
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static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
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static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
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