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rearrange some code, no functionality change.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48101 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2008-03-09 07:58:04 +00:00
parent d9c4c450bf
commit 90b347dc90
1 changed files with 59 additions and 58 deletions
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117
lib/Target/X86/X86InstrInfo.cpp
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@ -1404,67 +1404,68 @@ void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC, const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const { const TargetRegisterClass *SrcRC) const {
if (DestRC != SrcRC) { if (DestRC == SrcRC) {
// Moving EFLAGS to / from another register requires a push and a pop. unsigned Opc;
if (SrcRC == &X86::CCRRegClass) { if (DestRC == &X86::GR64RegClass) {
assert(SrcReg == X86::EFLAGS); Opc = X86::MOV64rr;
if (DestRC == &X86::GR64RegClass) { } else if (DestRC == &X86::GR32RegClass) {
BuildMI(MBB, MI, get(X86::PUSHFQ)); Opc = X86::MOV32rr;
BuildMI(MBB, MI, get(X86::POP64r), DestReg); } else if (DestRC == &X86::GR16RegClass) {
return; Opc = X86::MOV16rr;
} else if (DestRC == &X86::GR32RegClass) { } else if (DestRC == &X86::GR8RegClass) {
BuildMI(MBB, MI, get(X86::PUSHFD)); Opc = X86::MOV8rr;
BuildMI(MBB, MI, get(X86::POP32r), DestReg); } else if (DestRC == &X86::GR32_RegClass) {
return; Opc = X86::MOV32_rr;
} } else if (DestRC == &X86::GR16_RegClass) {
} else if (DestRC == &X86::CCRRegClass) { Opc = X86::MOV16_rr;
assert(DestReg == X86::EFLAGS); } else if (DestRC == &X86::RFP32RegClass) {
if (SrcRC == &X86::GR64RegClass) { Opc = X86::MOV_Fp3232;
BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg); } else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) {
BuildMI(MBB, MI, get(X86::POPFQ)); Opc = X86::MOV_Fp6464;
return; } else if (DestRC == &X86::RFP80RegClass) {
} else if (SrcRC == &X86::GR32RegClass) { Opc = X86::MOV_Fp8080;
BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg); } else if (DestRC == &X86::FR32RegClass) {
BuildMI(MBB, MI, get(X86::POPFD)); Opc = X86::FsMOVAPSrr;
return; } else if (DestRC == &X86::FR64RegClass) {
} Opc = X86::FsMOVAPDrr;
} else if (DestRC == &X86::VR128RegClass) {
Opc = X86::MOVAPSrr;
} else if (DestRC == &X86::VR64RegClass) {
Opc = X86::MMX_MOVQ64rr;
} else {
assert(0 && "Unknown regclass");
abort();
} }
cerr << "Not yet supported!"; BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg);
abort(); return;
} }
unsigned Opc; // Moving EFLAGS to / from another register requires a push and a pop.
if (DestRC == &X86::GR64RegClass) { if (SrcRC == &X86::CCRRegClass) {
Opc = X86::MOV64rr; assert(SrcReg == X86::EFLAGS);
} else if (DestRC == &X86::GR32RegClass) { if (DestRC == &X86::GR64RegClass) {
Opc = X86::MOV32rr; BuildMI(MBB, MI, get(X86::PUSHFQ));
} else if (DestRC == &X86::GR16RegClass) { BuildMI(MBB, MI, get(X86::POP64r), DestReg);
Opc = X86::MOV16rr; return;
} else if (DestRC == &X86::GR8RegClass) { } else if (DestRC == &X86::GR32RegClass) {
Opc = X86::MOV8rr; BuildMI(MBB, MI, get(X86::PUSHFD));
} else if (DestRC == &X86::GR32_RegClass) { BuildMI(MBB, MI, get(X86::POP32r), DestReg);
Opc = X86::MOV32_rr; return;
} else if (DestRC == &X86::GR16_RegClass) { }
Opc = X86::MOV16_rr; } else if (DestRC == &X86::CCRRegClass) {
} else if (DestRC == &X86::RFP32RegClass) { assert(DestReg == X86::EFLAGS);
Opc = X86::MOV_Fp3232; if (SrcRC == &X86::GR64RegClass) {
} else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) { BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg);
Opc = X86::MOV_Fp6464; BuildMI(MBB, MI, get(X86::POPFQ));
} else if (DestRC == &X86::RFP80RegClass) { return;
Opc = X86::MOV_Fp8080; } else if (SrcRC == &X86::GR32RegClass) {
} else if (DestRC == &X86::FR32RegClass) { BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg);
Opc = X86::FsMOVAPSrr; BuildMI(MBB, MI, get(X86::POPFD));
} else if (DestRC == &X86::FR64RegClass) { return;
Opc = X86::FsMOVAPDrr; }
} else if (DestRC == &X86::VR128RegClass) {
Opc = X86::MOVAPSrr;
} else if (DestRC == &X86::VR64RegClass) {
Opc = X86::MMX_MOVQ64rr;
} else {
assert(0 && "Unknown regclass");
abort();
} }
BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg); cerr << "Not yet supported!";
abort();
} }
static unsigned getStoreRegOpcode(const TargetRegisterClass *RC, static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,