6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-28 04:33:05 +00:00
Code Issues Projects Releases Wiki Activity

Fix delay slot filler for non mips1 targets. Patch by Akira Hatanaka

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121376 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2010-12-09 17:31:11 +00:00
parent 7d17097e4a
commit 90c595425b
1 changed files with 9 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
lib/Target/Mips/MipsDelaySlotFiller.cpp
View File

@ -31,7 +31,7 @@ namespace {
const TargetInstrInfo *TII;
static char ID;
Filler(TargetMachine &tm)
Filler(TargetMachine &tm)
: MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
virtual const char *getPassName() const {
@ -55,18 +55,22 @@ namespace {
/// Currently, we fill delay slots with NOPs. We assume there is only one
/// delay slot per delayed instruction.
bool Filler::
runOnMachineBasicBlock(MachineBasicBlock &MBB)
runOnMachineBasicBlock(MachineBasicBlock &MBB)
{
bool Changed = false;
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
if (TM.getSubtarget<MipsSubtarget>().isMips1() &&
I->getDesc().hasDelaySlot()) {
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
const TargetInstrDesc& Tid = I->getDesc();
if (Tid.hasDelaySlot() &&
(TM.getSubtarget<MipsSubtarget>().isMips1() ||
Tid.isCall() || Tid.isBranch() || Tid.isReturn())) {
MachineBasicBlock::iterator J = I;
++J;
BuildMI(MBB, J, I->getDebugLoc(), TII->get(Mips::NOP));
++FilledSlots;
Changed = true;
}
}
return Changed;
}