6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-09-24 23:28:41 +00:00
Code Issues Projects Releases Wiki Activity

Remove extra semi-colons.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151169 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier
2012-02-22 17:25:00 +00:00
parent 91ba63d230
commit 90f20044ad
7 changed files with 9 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Analysis/RegionInfo.cpp
View File

@@ -650,7 +650,7 @@ void RegionInfo::buildRegionsTree(DomTreeNode *N, Region *region) {
// This basic block is a start block of a region. It is already in the // This basic block is a start block of a region. It is already in the
// BBtoRegion relation. Only the child basic blocks have to be updated. // BBtoRegion relation. Only the child basic blocks have to be updated.
if (it != BBtoRegion.end()) { if (it != BBtoRegion.end()) {
Region *newRegion = it->second;; Region *newRegion = it->second;
region->addSubRegion(getTopMostParent(newRegion)); region->addSubRegion(getTopMostParent(newRegion));
region = newRegion; region = newRegion;
} else { } else {

4
lib/CodeGen/BranchFolding.cpp
View File

@@ -1111,7 +1111,7 @@ ReoptimizeBlock:
} }
} }
PrevBB.splice(PrevBB.end(), MBB, MBB->begin(), MBB->end()); PrevBB.splice(PrevBB.end(), MBB, MBB->begin(), MBB->end());
PrevBB.removeSuccessor(PrevBB.succ_begin());; PrevBB.removeSuccessor(PrevBB.succ_begin());
assert(PrevBB.succ_empty()); assert(PrevBB.succ_empty());
PrevBB.transferSuccessors(MBB); PrevBB.transferSuccessors(MBB);
MadeChange = true; MadeChange = true;
@@ -1670,7 +1670,7 @@ bool BranchFolder::HoistCommonCodeInSuccs(MachineBasicBlock *MBB) {
LocalDefsSet.insert(*OR); LocalDefsSet.insert(*OR);
} }
HasDups = true;; HasDups = true;
++TIB; ++TIB;
++FIB; ++FIB;
} }

2
lib/Support/DataExtractor.cpp
View File

@@ -75,7 +75,7 @@ uint32_t DataExtractor::getU32(uint32_t *offset_ptr) const {
uint32_t *DataExtractor::getU32(uint32_t *offset_ptr, uint32_t *dst, uint32_t *DataExtractor::getU32(uint32_t *offset_ptr, uint32_t *dst,
uint32_t count) const { uint32_t count) const {
return getUs<uint32_t>(offset_ptr, dst, count, this, IsLittleEndian, return getUs<uint32_t>(offset_ptr, dst, count, this, IsLittleEndian,
Data.data());; Data.data());
} }
uint64_t DataExtractor::getU64(uint32_t *offset_ptr) const { uint64_t DataExtractor::getU64(uint32_t *offset_ptr) const {

2
lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@@ -779,7 +779,7 @@ int64_t ARMBaseRegisterInfo::
getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
const MCInstrDesc &Desc = MI->getDesc(); const MCInstrDesc &Desc = MI->getDesc();
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
int64_t InstrOffs = 0;; int64_t InstrOffs = 0;
int Scale = 1; int Scale = 1;
unsigned ImmIdx = 0; unsigned ImmIdx = 0;
switch (AddrMode) { switch (AddrMode) {

4
lib/Target/MSP430/MSP430ISelLowering.cpp
View File

@@ -644,7 +644,7 @@ SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy()); SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);; return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);
} }
SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op, SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op,
@@ -653,7 +653,7 @@ SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op,
const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), /*isTarget=*/true); SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), /*isTarget=*/true);
return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);; return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);
} }
static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC, static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,

2
lib/Target/X86/X86Subtarget.cpp
View File

@@ -302,7 +302,7 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
} }
// FIXME: AVX2 codegen support is not ready. // FIXME: AVX2 codegen support is not ready.
//if ((EBX >> 5) & 0x1) { //if ((EBX >> 5) & 0x1) {
// X86SSELevel = AVX2;; // X86SSELevel = AVX2;
// ToggleFeature(X86::FeatureAVX2); // ToggleFeature(X86::FeatureAVX2);
//} //}
if ((EBX >> 8) & 0x1) { if ((EBX >> 8) & 0x1) {

2
lib/VMCore/GCOV.cpp
View File

@@ -107,7 +107,7 @@ bool GCOVFunction::read(GCOVBuffer &Buff, GCOVFormat Format) {
for (unsigned i = 0, e = Count; i != e; ++i) { for (unsigned i = 0, e = Count; i != e; ++i) {
Blocks[i]->addCount(Buff.readInt64()); Blocks[i]->addCount(Buff.readInt64());
} }
return true;; return true;
} }
LineNumber = Buff.readInt(); LineNumber = Buff.readInt();