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ARM vmla/vmls assembly parsing for the lane index operand.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142389 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-10-18 18:27:07 +00:00
parent e8692ed5a6
commit 9120088979
3 changed files with 16 additions and 12 deletions
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16
lib/Target/ARM/ARMInstrNEON.td
View File

@ -2095,9 +2095,9 @@ class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
: N3VLane32<0, 1, op21_20, op11_8, 1, 0,
(outs DPR:$Vd),
(ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
(ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
NVMulSLFrm, itin,
OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
[(set (Ty DPR:$Vd),
(Ty (ShOp (Ty DPR:$src1),
(Ty (MulOp DPR:$Vn,
@ -2108,9 +2108,9 @@ class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
ValueType Ty, SDNode MulOp, SDNode ShOp>
: N3VLane16<0, 1, op21_20, op11_8, 1, 0,
(outs DPR:$Vd),
(ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
(ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
NVMulSLFrm, itin,
OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
[(set (Ty DPR:$Vd),
(Ty (ShOp (Ty DPR:$src1),
(Ty (MulOp DPR:$Vn,
@ -2130,9 +2130,9 @@ class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
SDPatternOperator MulOp, SDPatternOperator ShOp>
: N3VLane32<1, 1, op21_20, op11_8, 1, 0,
(outs QPR:$Vd),
(ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
(ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
NVMulSLFrm, itin,
OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
[(set (ResTy QPR:$Vd),
(ResTy (ShOp (ResTy QPR:$src1),
(ResTy (MulOp QPR:$Vn,
@ -2144,9 +2144,9 @@ class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
SDNode MulOp, SDNode ShOp>
: N3VLane16<1, 1, op21_20, op11_8, 1, 0,
(outs QPR:$Vd),
(ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
(ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
NVMulSLFrm, itin,
OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
[(set (ResTy QPR:$Vd),
(ResTy (ShOp (ResTy QPR:$src1),
(ResTy (MulOp QPR:$Vn,

4
test/MC/ARM/neon-mul-accum-encoding.s
View File

@ -8,6 +8,7 @@
vmla.i16 q9, q8, q10
vmla.i32 q9, q8, q10
vmla.f32 q9, q8, q10
vmla.i32 q12, q8, d3[0]
@ CHECK: vmla.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf2]
@ CHECK: vmla.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf2]
@ -17,6 +18,7 @@
@ CHECK: vmla.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xf2]
@ CHECK: vmla.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf2]
@ CHECK: vmla.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x40,0xf2]
@ CHECK: vmla.i32 q12, q8, d3[0] @ encoding: [0xc3,0x80,0xe0,0xf3]
vmlal.s8 q8, d19, d18
@ -57,6 +59,7 @@
vmls.i16 q9, q8, q10
vmls.i32 q9, q8, q10
vmls.f32 q9, q8, q10
vmls.i16 q4, q12, d6[2]
@ CHECK: vmls.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf3]
@ CHECK: vmls.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf3]
@ -66,6 +69,7 @@
@ CHECK: vmls.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xf3]
@ CHECK: vmls.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf3]
@ CHECK: vmls.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x60,0xf2]
@ CHECK: vmls.i16 q4, q12, d6[2] @ encoding: [0xe6,0x84,0x98,0xf3]
vmlsl.s8 q8, d19, d18

8
test/MC/ARM/neont2-mul-accum-encoding.s
View File

@ -10,7 +10,7 @@
vmla.i16 q9, q8, q10
vmla.i32 q9, q8, q10
vmla.f32 q9, q8, q10
@ vmla.i32 q12, q8, d3[0]
vmla.i32 q12, q8, d3[0]
@ CHECK: vmla.i8 d16, d18, d17 @ encoding: [0x42,0xef,0xa1,0x09]
@ CHECK: vmla.i16 d16, d18, d17 @ encoding: [0x52,0xef,0xa1,0x09]
@ -20,7 +20,7 @@
@ CHECK: vmla.i16 q9, q8, q10 @ encoding: [0x50,0xef,0xe4,0x29]
@ CHECK: vmla.i32 q9, q8, q10 @ encoding: [0x60,0xef,0xe4,0x29]
@ CHECK: vmla.f32 q9, q8, q10 @ encoding: [0x40,0xef,0xf4,0x2d]
@ FIXME: vmla.i32 q12, q8, d3[0] @ encoding: [0xe0,0xff,0xc3,0x80]
@ CHECK: vmla.i32 q12, q8, d3[0] @ encoding: [0xe0,0xff,0xc3,0x80]
vmlal.s8 q8, d19, d18
@ -63,7 +63,7 @@
vmls.i16 q9, q8, q10
vmls.i32 q9, q8, q10
vmls.f32 q9, q8, q10
@ vmls.i16 q4, q12, d6[2]
vmls.i16 q4, q12, d6[2]
@ CHECK: vmls.i8 d16, d18, d17 @ encoding: [0x42,0xff,0xa1,0x09]
@ CHECK: vmls.i16 d16, d18, d17 @ encoding: [0x52,0xff,0xa1,0x09]
@ -73,7 +73,7 @@
@ CHECK: vmls.i16 q9, q8, q10 @ encoding: [0x50,0xff,0xe4,0x29]
@ CHECK: vmls.i32 q9, q8, q10 @ encoding: [0x60,0xff,0xe4,0x29]
@ CHECK: vmls.f32 q9, q8, q10 @ encoding: [0x60,0xef,0xf4,0x2d]
@ FIXME: vmls.i16 q4, q12, d6[2] @ encoding: [0x98,0xff,0xe6,0x94]
@ CHECK: vmls.i16 q4, q12, d6[2] @ encoding: [0x98,0xff,0xe6,0x84]
vmlsl.s8 q8, d19, d18