diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp index 3ee0bd57bc1..b1ac4a6f277 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp @@ -57,13 +57,13 @@ static unsigned getFixupKindNumBytes(unsigned Kind) { case FK_Data_1: return 1; case FK_Data_2: + case PPC::fixup_ppc_ha16: + case PPC::fixup_ppc_lo16: + case PPC::fixup_ppc_lo16_ds: return 2; case FK_Data_4: case PPC::fixup_ppc_brcond14: case PPC::fixup_ppc_br24: - case PPC::fixup_ppc_ha16: - case PPC::fixup_ppc_lo16: - case PPC::fixup_ppc_lo16_ds: return 4; case FK_Data_8: return 8; @@ -100,9 +100,9 @@ public: // name offset bits flags { "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_ppc_lo16", 16, 16, 0 }, - { "fixup_ppc_ha16", 16, 16, 0 }, - { "fixup_ppc_lo16_ds", 16, 14, 0 }, + { "fixup_ppc_lo16", 0, 16, 0 }, + { "fixup_ppc_ha16", 0, 16, 0 }, + { "fixup_ppc_lo16_ds", 0, 14, 0 }, { "fixup_ppc_tlsreg", 0, 0, 0 }, { "fixup_ppc_nofixup", 0, 0, 0 } }; diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp index 7a84723ed56..c09ae0e2cad 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp @@ -33,7 +33,6 @@ namespace { virtual const MCSymbol *undefinedExplicitRelSym(const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const; - virtual void adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset); virtual void sortRelocs(const MCAssembler &Asm, std::vector &Relocs); @@ -240,19 +239,6 @@ const MCSymbol *PPCELFObjectWriter::undefinedExplicitRelSym(const MCValue &Targe return NULL; } -void PPCELFObjectWriter:: -adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset) { - switch ((unsigned)Fixup.getKind()) { - case PPC::fixup_ppc_ha16: - case PPC::fixup_ppc_lo16: - case PPC::fixup_ppc_lo16_ds: - RelocOffset += 2; - break; - default: - break; - } -} - // The standard sorter only sorts on the r_offset field, but PowerPC can // have multiple relocations at the same offset. Sort secondarily on the // relocation type to avoid nondeterminism. diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp index 2223cd623cb..3f04a4ec0ae 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp @@ -142,7 +142,7 @@ unsigned PPCMCCodeEmitter::getHA16Encoding(const MCInst &MI, unsigned OpNo, if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); // Add a fixup for the branch target. - Fixups.push_back(MCFixup::Create(0, MO.getExpr(), + Fixups.push_back(MCFixup::Create(2, MO.getExpr(), (MCFixupKind)PPC::fixup_ppc_ha16)); return 0; } @@ -153,7 +153,7 @@ unsigned PPCMCCodeEmitter::getLO16Encoding(const MCInst &MI, unsigned OpNo, if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); // Add a fixup for the branch target. - Fixups.push_back(MCFixup::Create(0, MO.getExpr(), + Fixups.push_back(MCFixup::Create(2, MO.getExpr(), (MCFixupKind)PPC::fixup_ppc_lo16)); return 0; } @@ -170,7 +170,7 @@ unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo, return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits; // Add a fixup for the displacement field. - Fixups.push_back(MCFixup::Create(0, MO.getExpr(), + Fixups.push_back(MCFixup::Create(2, MO.getExpr(), (MCFixupKind)PPC::fixup_ppc_lo16)); return RegBits; } @@ -188,7 +188,7 @@ unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo, return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits; // Add a fixup for the displacement field. - Fixups.push_back(MCFixup::Create(0, MO.getExpr(), + Fixups.push_back(MCFixup::Create(2, MO.getExpr(), (MCFixupKind)PPC::fixup_ppc_lo16_ds)); return RegBits; } diff --git a/test/MC/PowerPC/ppc64-fixups.s b/test/MC/PowerPC/ppc64-fixups.s index 281dce3f9e7..06b2ffd303c 100644 --- a/test/MC/PowerPC/ppc64-fixups.s +++ b/test/MC/PowerPC/ppc64-fixups.s @@ -8,113 +8,113 @@ # FIXME: .TOC.@tocbase # CHECK: li 3, target@l # encoding: [0x38,0x60,A,A] -# CHECK-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_lo16 -# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_LO target 0x0 +# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_lo16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0 li 3, target@l # CHECK: addis 3, 3, target@ha # encoding: [0x3c,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 0, value: target@ha, kind: fixup_ppc_ha16 -# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_HA target 0x0 +# CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_ha16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0 addis 3, 3, target@ha # CHECK: lis 3, target@ha # encoding: [0x3c,0x60,A,A] -# CHECK-NEXT: # fixup A - offset: 0, value: target@ha, kind: fixup_ppc_ha16 -# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_HA target 0x0 +# CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_ha16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0 lis 3, target@ha # CHECK: addi 4, 3, target@l # encoding: [0x38,0x83,A,A] -# CHECK-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_lo16 -# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_LO target 0x0 +# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_lo16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0 addi 4, 3, target@l # CHECK: lwz 1, target@l(3) # encoding: [0x80,0x23,A,A] -# CHECK-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_lo16 -# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_LO target 0x0 +# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_lo16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0 lwz 1, target@l(3) # CHECK: ld 1, target@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_lo16_ds -# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_LO_DS target 0x0 +# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_lo16_ds +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO_DS target 0x0 ld 1, target@l(3) # CHECK: ld 1, target@toc(2) # encoding: [0xe8,0x22,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target@toc, kind: fixup_ppc_lo16_ds -# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_DS target 0x0 +# CHECK-NEXT: # fixup A - offset: 2, value: target@toc, kind: fixup_ppc_lo16_ds +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_DS target 0x0 ld 1, target@toc(2) # CHECK: addis 3, 2, target@toc@ha # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 0, value: target@toc@ha, kind: fixup_ppc_ha16 -# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA target 0x0 +# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@ha, kind: fixup_ppc_ha16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_HA target 0x0 addis 3, 2, target@toc@ha # CHECK: addi 4, 3, target@toc@l # encoding: [0x38,0x83,A,A] -# CHECK-NEXT: # fixup A - offset: 0, value: target@toc@l, kind: fixup_ppc_lo16 -# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO target 0x0 +# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_lo16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO target 0x0 addi 4, 3, target@toc@l # CHECK: lwz 1, target@toc@l(3) # encoding: [0x80,0x23,A,A] -# CHECK-NEXT: # fixup A - offset: 0, value: target@toc@l, kind: fixup_ppc_lo16 -# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO target 0x0 +# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_lo16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO target 0x0 lwz 1, target@toc@l(3) # CHECK: ld 1, target@toc@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target@toc@l, kind: fixup_ppc_lo16_ds -# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS target 0x0 +# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_lo16_ds +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO_DS target 0x0 ld 1, target@toc@l(3) # FIXME: @tls # CHECK: addis 3, 2, target@tprel@ha # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 0, value: target@tprel@ha, kind: fixup_ppc_ha16 -# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TPREL16_HA target 0x0 +# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@ha, kind: fixup_ppc_ha16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HA target 0x0 addis 3, 2, target@tprel@ha # CHECK: addi 3, 3, target@tprel@l # encoding: [0x38,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 0, value: target@tprel@l, kind: fixup_ppc_lo16 -# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TPREL16_LO target 0x0 +# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@l, kind: fixup_ppc_lo16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_LO target 0x0 addi 3, 3, target@tprel@l # CHECK: addis 3, 2, target@dtprel@ha # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 0, value: target@dtprel@ha, kind: fixup_ppc_ha16 -# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_DTPREL16_HA target 0x0 +# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@ha, kind: fixup_ppc_ha16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HA target 0x0 addis 3, 2, target@dtprel@ha # CHECK: addi 3, 3, target@dtprel@l # encoding: [0x38,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 0, value: target@dtprel@l, kind: fixup_ppc_lo16 -# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_DTPREL16_LO target 0x0 +# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@l, kind: fixup_ppc_lo16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_LO target 0x0 addi 3, 3, target@dtprel@l # CHECK: addis 3, 2, target@got@tprel@ha # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 0, value: target@got@tprel@ha, kind: fixup_ppc_ha16 -# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_HA target 0x0 +# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel@ha, kind: fixup_ppc_ha16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_HA target 0x0 addis 3, 2, target@got@tprel@ha # CHECK: ld 1, target@got@tprel@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] -# CHECK-NEXT: # fixup A - offset: 0, value: target@got@tprel@l, kind: fixup_ppc_lo16_ds -# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_LO_DS target 0x0 +# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel@l, kind: fixup_ppc_lo16_ds +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_LO_DS target 0x0 ld 1, target@got@tprel@l(3) # CHECK: addis 3, 2, target@got@tlsgd@ha # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 0, value: target@got@tlsgd@ha, kind: fixup_ppc_ha16 -# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_HA target 0x0 +# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@ha, kind: fixup_ppc_ha16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_HA target 0x0 addis 3, 2, target@got@tlsgd@ha # CHECK: addi 3, 3, target@got@tlsgd@l # encoding: [0x38,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 0, value: target@got@tlsgd@l, kind: fixup_ppc_lo16 -# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_LO target 0x0 +# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@l, kind: fixup_ppc_lo16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_LO target 0x0 addi 3, 3, target@got@tlsgd@l # CHECK: addis 3, 2, target@got@tlsld@ha # encoding: [0x3c,0x62,A,A] -# CHECK-NEXT: # fixup A - offset: 0, value: target@got@tlsld@ha, kind: fixup_ppc_ha16 -# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_HA target 0x0 +# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsld@ha, kind: fixup_ppc_ha16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_HA target 0x0 addis 3, 2, target@got@tlsld@ha # CHECK: addi 3, 3, target@got@tlsld@l # encoding: [0x38,0x63,A,A] -# CHECK-NEXT: # fixup A - offset: 0, value: target@got@tlsld@l, kind: fixup_ppc_lo16 -# CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_LO target 0x0 +# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsld@l, kind: fixup_ppc_lo16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_LO target 0x0 addi 3, 3, target@got@tlsld@l